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I've heard that Verilog is used almost exclusively to the West of the Mississippi river, and VHDL to the East.

 

Personally, I started with Verilog, and I am East of the Mississippi river...

Blogger

Looking to use the NI myRIO device with its dual-core ARM A9 and customizable Xilinx FPGA on a project soon...

Rookie

Good second day.  Look forward to tomorrow.

Rookie

I've been in engineering for 15+ years.

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I determine VHDL or Verilog as the application and complexity determines.

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I'm leaning toward VHDL but learning something from Verilog too.

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I know the difference between HDL's and programming languages. 

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Understand the difference.

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I program in C+ .Net, C#.Net, Assembler, and VB6. I currently designing a PCB targeted at automotive M2M.

I am looking at a built-in-self-test for the product. I do not have a any 'battle' experience with FPGAs or ASICs to speak of. Can an FPGA/ASIC be employed as the core of the built-in-self-test test structure.

Any pointers or comments would be most appreciated.

Many thanks folks.

Ron Boyce (Birmingham UK)

e-mail: rnboyc@aol.com

 

Rookie

I am OK with both languages

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I am in both VHDL & Verilog camps - been designing with both.

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Trying to catchup Max's seminars.

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C, C+, C , C#, VHDL and Verilog

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Thank you for the presentation.

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Presentation is great, good addition to my knowledge of FPGA/VHDL

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In engineering 10+ years

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Combination of both 

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Have experience with VHDL, C, and C+

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I'm familiar with both VHDL and Verilog, C and C+ . I studied C and C at university and subsequently in my professional life have used both VHDL and Verilog to design ASICs and FPGAs.

informative session

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hello, late but better than never, from Edmonton, Alberta

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Good Morning from San Jose, CA.

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Thanks Max; excellent presentation

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I'm mechatronics Engineer

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as for open source tools "icarus verilog" and "gtkwave" are verilog simulator and wave viewer respectively. i found this on the website mentioned below.

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@link2sriram i found this site quite helpful-www.asic-world.com.tutorials for vhdl,verilog,systemverilog and also verification languages can be found.

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Good to be aboard again, business caused me to get online archival session today.

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HDL's and programming languages, all new to me. I had some boolean algebra, binary math and

other numbering systems, even some machine languages long ago in the early 70s.

   I need late model code for todays MCUs etc. Thank you.

Rookie

waiting for the answers till tommorow. thank u for ythe session max. bye.

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any websites containig tutorials on hdl?

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please recommend some books for learning HDL

 

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which is easier to learn verilo hdl or VHDL

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are ther open source packages for writing in HDL

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Been in engineering only since  88. Just a newbie!

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Application vs Complexity- I also consider the speed to complete a tast, to know whether to write a procedure in a lower level language, for the fastest operation.

 

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OH -- I'm off to get back to work -- I look forward to seeing everyone tomorrow -- Max

@credit: On the xilinx, how do you call fpga functions from your software,that is running on the arm?

Good question -- go to www.AllProgrammablePlanet.com and check out Jeremy Smith's column from yesterday about the use of the AXI buses

On the xilinx, how do you call fpga functions from your software,that is running on the arm?
Rookie
Any one used lava or wired? Haskell embedded hdl.
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Thanks a lot..........waiting for next one

 

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@moncho: "which slice?"

Are you asking what I mean by the term "slice" like "DSP Slice"? -- it's just a term we (FPGA folks) use like "DSP block"

Thanks a lot :) Looking forward to the next lectures !

Rookie

@Torgy: You are based here in Huntsville AL?

 

Thanks to everyone for joining -- and thanks also for the kond words --- sorry it takes me so long to respond to questions (I'm a 2-fingered "hunt and peck" typist :-)

Thank you for the lecture Max

Rookie

@Ash88: Which one is getting more attention to enhance and improve and which one do you think will dominate :)

Historically there's been an inertic when it comes to moving forward. When Verilog and VHDL an dSynthesis firtst came out, designers said that they could create better designs by hand working at the gate level. But that's only true when you are working with a limited numbert of gates. When you are deallling with 100,000+ gates, you can experiment with your RTL and synthesise it much quicker.


Now we have C/C== and HLS (which as I say is used to generate VHDL/Verilog and output) -- some people a reluctant to use it, but others are using it to create really REALLY big designs...

Yes, me too, I was really looking forward to Wednesday session ... but, when the CFO calls a meeting, well... you know.   I will definitely be back on Thursday and Friday both ...

Rookie

Thanks for the stimulating lecture Dr. Maxfield. Nice work!

 

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Thansk Mark -- sorry you'll miss tomorrow -- hopefully you'll be back on Thursday and Friday :-)

So we can design either in C/C+ or Verilog/VHDL. Which one is getting more attention to enhance and improve and which one do you think will dominate :) ?

Rookie

@Ankit: "how  all programmable devices consume less power?"

This is a complicated question. An ASIC/SoC uses the least power and gives the best performance, but it costs millions of dollars and takes at least a year (maybe two) to design and build. An FPGA consumes more power and offers less performance than an ASIC/SoC, but you can implement a design much faster and cheaper.

A microprocessor/microcontroller is really cheap, and great at implementing decision-making software, but it' svery ineffuicient at performing algorithmic data processing tasks. An FPGA can perform algorithmic dataprocessing tasks at a lower clock rate using less power because it can do things in a massivelt parallel fashion

Thank you Max and Brian.  Unfortunately I miss tomorrows live broadcast session on Tools and Methodolgies, my area of expertise ... due to a late schedule change.  Dang ... and may not even be able to get back 'online' quickly enough for the post braodcast Q&A ...  but I will listen to the audio portion.  Thank you for taking the time to address the Q&A's.

Rookie

@Ash99: "What's the future of HDL? HLS or RTL ?"

HLS refers to a form of synthesis technology, RTL refers to a level of design abstraction. HLS takes a C/C+ description and generates RTL (in the form of Verilog or VHDL) -- thsi RTL is then "consumed" by regular logic synthesis

@bobolicious: "Is one programming language better for certain device families or for a particular manufacture, i.e. Xilinx vs Altera?"

No -- they both accept either language -- the languages are parsed and read into a data structure from whence they are processed (simulated, synthesized) 

What's the future of HDL? HLS or RTL ?

Rookie

Thanks Max! see you tomorrow

Rookie

how  all programmable devices consume less power?

 

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Personally I find SystemVerilog quite comfortable to work with (my experience is mostly with synthesis, rather than verification). It has enough support for low-level stuff (down to the transistor level) and high-level abstractions (even structured data types and object orientation). Add to that general industry support (and investment) and you have a clear winner. I see the subject of Verilog vs. VHDL in the same way as the old C vs. Pascal conflict from the 80s.

Rookie

@mginyane: "Can you design with FPGA without synthesizing?"

Well, you can capture a design and simulate it -- but you can't load it into the FPGA unless you synthesise it into a configuration file

In today's lecture, it was a bit unclear to me regarding slides 4, 5, 6 ... and later slide 12.  I agree what was said regarding slide 4 -- that at the end of execution, both registers will contain the value 6.  However, it appears to me that this is NOT the case for slide 5 with common clock (seems that registers will swap values with each clock cycle).  And what about slide 6 ... depends on whether the last 2 instructions are executed sequentially or concurrently ?  Similarly, for slide 12 (& slide 13).  With a common clock, what happens to blocks B, C, & D during the first 3 clock cycles until the pipeline is "loaded".  Are we to assign some initial conditions to the appropriate registers (during power-on-reset or equivalent) such that whatever values reside on the output registers are loaded into the successive register -- until the first 4 clock cycles are finally achieved ?  I am an analog engineer, dabbling here.  Thanks.

Rookie

@Bill_Devine the level of abstraction of computer science need to be most high, because the HDL is at level low so is description of hardware.

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@lleiva: "the synthesis from C/C+ is effective in terms of time and area? "

The big advantage of HLS (sythesis from C/C ) is that it allows you to explore lots of different implementation options -- you can make something very area effcients (by resource sharing) but have lower performance, or use a lot of area (resources in FPGA terms) and have higher performance -- like all engineering it's a tradeoff

the logic device just performs logic on whatever data is presented at a certain port

@Bill_Devine the level of abstraction of computer science need to be most high, because the HDL is at level low so is description of hardware.

Rookie

well in HDL time sequencing of data is an external process

Can you design with FPGA without synthesizing?

Rookie

Is one programming language better for certain device families or for a particular manufacture, i.e. Xilinx vs Altera?

Rookie

@ghosh: "What did those arrows signify in slide 19?"

Go to www.AllProgrammablePlanet.com and search for "Verilog & VHDL" and read Parts 1, 2, and 3 and all will become clear :-)

Dave:  Time sequenced or concurrent?

 

Rookie

@Cristian: "Is EDA community waiting/seeking for a new better HDL?"

Hard to say -- there are some issues with VHDL and Verilog that are confusing -- like "assignments" -- you have to remember that these languages are 20 years old now. Languages like MyHDL are based on newer concepts that make them easier to understand and use -- but there's a lot of "inertia" when it comes to moving to something new

the synthesis from C/C+ is effective in terms of time and area? 

Rookie

Ghosh ... certainly not a detailed all inclusive one ... but ... give 'em some credit for getting it online and causing you to think about it.

Rookie

What's the future of HDL ? High-level ? RTL ?

Rookie

This does not seem to be a good format for getting any answer!!!

 

Rookie

@lucava: Re your question "Question: why are the different blocks not loaded with data at clock #1 ?"

Tis is a good question -- in fact they are all loaded at clock #1, the problem is that before clock #1 they all contain random "stuff" -- on click #1 we load the "good" values from the inputs into blovk A, and the random/unknown values from block A into Block B .. as we ckke on clocking things we get rid of the unknown / random values

Slide 13: What are the outputs of blocks B,C&D at clock 1?

Rookie

Great presentation!

What is the advantage of two different clocks?

Rookie

Thank you Max, very interesting today.  Also, I suggest the following text for learning python: http://www.greenteapress.com/thinkpython/html/index.html

Rookie

Is EDA community waiting/seeking for a new better HDL?

Rookie

sorry, that was with regards to the languge used in programming flga's

 

Rookie

what is the need of RTL description

i mean where it is needed

Rookie

 should be very interesting.    Brian, has the session for the 10 minutes on why "Mine is the best ... ",  already been established ?

Rookie

If you go to APP (www.AllProgrammablePlanet.com) and so a search on "Verilog & VHDL" you will find a lot of the stuff I covered here explained in much more detail.

Thanks a lot. This session was really helpful

Rookie

thank you max.... good precentation

Rookie

Slide 13.

Question: why are the different blocks not loaded with data at clock #1 ?

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Thanks  This affirmed my understanding!

 

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I just recieved and Altera NIOS 2 Cyclone III kit and these lectures are helping me to bend my head in the right direction to engage with it.  Thanks 

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What did those arrows signify in slide 19?

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Thank you max and at all the people

Rookie

Max, can we use your slides for teaching purposes?

slide13:
question:whyarethedifferentblocks notloadedwithdataatclock#1?
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thanks max

cleared my doubts

Rookie

great lecture. yeah they helped me alot.
Thanks

Rookie

The website I mentioned is www.AllProgrammablePlanet.com

 

Thanks Max and company.

Rookie

I can't uderstand the concepts on slide 15-17

Rookie

I understand that currently the HLS languages are a strong trend, but the synthesized design is effective in terms of time and area? 

Rookie

nice example, its now clear

Rookie

Yes, very informative... would love to see some actual examples of parallelism within HDL

Rookie

Thanks Max, A nice presentation.

Rookie

This was a good exposure. Not being a programmer, most of this is new for me.

Rookie

Thanks Max and host Brian !!!

Rookie

Good overview. Do we get more details?

Rookie

What was the website Max mentioned?

 

Rookie

Nice slideshow. Understood. Thanks Max!

Rookie

@max Many thanks I think i am getting my head straight at last

CEO

quito-ecuador, electronic engeneer automatic and control specialist, but im investigate about the new paradig to interconection in chip. Networks on Chip, and im usig fpga and vhdl

Great presentation - thanks!

Rookie

The discussion on why "Mine is the best ... " should be very interesting.    Brian, has the session already been estanblished ?

Rookie

slide13:
question:whyarethedifferentblocksnotlaodedwithdataatclock#1?
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@moncho: Google translates this to Max's native language as "not really, but if we see some of that". 

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10 min for each language! every interesting

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I can't understand the concepts from slide 15-17

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I can't understand the concepts from slide 15-17

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I studied VHDL using SOLO during my Degree in the early 90's

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I've always equated Verilog with logical synthesis as well.

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realmente no, pero si vemos algo de eso

Rookie

did not quite follow the thougts expressed in slide 19!!!

 

Rookie

disponen de la materia de co-diseno de hw/sw?

in  bucaramanga city

Rookie

universidad industrial de santander

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saludos moncho, en que instituto estudias?

i'm studing engineer electronic in colombia in the UIS

Rookie

computer science by training but I am EE enthusiastic and planning to do MSc in EE

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Have been writing embedded software in an ASIC/SoC design environment for about 11 years. The software has been targeted at hardware validation, hardware debug, as well as production software for the final end product.

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two years in engineering in india at national institiute of technology karnataka

Rookie

2 years in ASIC Design

 

Rookie

15+yrs in mostly software engineering

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5 years in rel and rad engineering

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Started 50 years ago. Gave it up for 35 years, now back for the last 5 years.

Rookie

13 years using vhdl

Rookie

Waaaay back when... 1970 'ish

Rookie

8 years as a full-time engineer (software for embedded processors) just getting started with FPGAs

 

Rookie

42 years, chip design

 

Rookie

Twenty years. First professional job was 1992.

Rookie

still in grad school!

Rookie

~ 15 years as a Systems Eng.

Rookie

I have been an engineer for 34 years

 

Rookie

Hardware and software 30 years

CEO

25 years ... mostly software

Rookie

good old object orientated coding

in the programing in C no existe parallelism, that is the advantage of the VHDL

Rookie

VHDL is a strongly "typed" language Verilog is more foregiving.

Rookie

I guess it is neither with complexity nor with application. its only with what we are most comfortable with !

Rookie

based on both application and complexity

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yes we can use model sim, you need to import the hw structure to model sim

Choose the language depending on the application complexity.

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can we use modelsim for schematic editor in xilinx?

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Many languages to solve many problem types

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yes, the language changes by the end application

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Yes, I try to chose the best language for the job

Rookie

C, C+ . Still learning Verilog & VHDL, no preference.

Rookie

Can we use MAX's slides for teaching purposes?

I prefer VHDL anyway

Rookie

model sim is a interesting form to simulate and modulated test benchs

SAB596 for the FPGA's of xilinx to use ISE for to program and the simulation in the testbench, can see graficatelly or for code VHDL

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Hafi'   check your browser is allowing scripts from blogtalkradio.com, techonline.com

 

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A testbench is simply a HDL module that instantiates the module you want to test and provides input stimulus.  It's just another .vhd or .v file.  Xilinx ISE can generate the basic skeleton for you.  Maybe Quartus can as well.

 

Rookie

so, basically job security.

 

Manager

test bench is also will be in some hdl language

Rookie

love the term ... Honking Big !!!

Rookie

i am not getting even audio

 

how can we create testbench?

Rookie

i am not able to get the lecture please help me

thanks again for your inputs!

Rookie

looks like today it is all very basic !

Rookie

Which one prefer Verilog or vhdl?

Rookie

The difference between synthesis and compilation: Compilation turns your code into an ordered sequence of instructions run by the processor.  Synthesis turns your HDL into what is essentially physical hardware - more equivalent to the processor itself than the instructions being run on it.

 

Rookie

late... but i'm here :)

Rookie

what is the difference  VHDL/verilog? I only had worked in VHDL

Rookie

Xilinx System Generator for simulink is great for getting going quickly.

Assembly and basic VHDL

 

Rookie

I've used both, but more VHDL.

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i am a bit unclear on synthesis

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My job is primarily writing software to run on existing silicon. C is the language I use for that. 

Rookie

read and write C, C+ ,  can read VHDL and Verilog

Rookie

How about if thers is a skew in CLOCK signal, passing into 2 registers?

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what is difference in synthesis and compiler

Rookie

vhdl

systemgenerator

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I did a litte VHDL in school but work in an all-verilog shop now.  We do use a few VHDL IP bits here and there.

Rookie

Assembler, pascal , basic VHDL

CEO

C, C+ , can read Verilog and VHDL

Rookie

I develop embedded systems in almost exclusively ANSI C...

Rookie

Designing in simulink but have done some editing in VHDL.

Verilog! I shifted from VHDL :)

 

Rookie

I'm American... so Verilog :-)

 

Manager

Started with VHDL and then switched to Verilog.

Rookie

@ Brain Fuller..Lot's of difference ..

 

Rookie

make sure your browser deosn't limit scripts running from blogtalkradio.com

 

Rookie

I do not know HDL but my degree is in Computer Science

Rookie

I guess I will have to wait until later

 

Rookie

@moncho slide* ;) too much of FPGA internals!! ha ha

Rookie

Thanks for your take on HDLs v. programming languages... looks like there may be a slight majority who are familiar with them.

Rookie

having the same issue I had yesterday I cannot listen to the live broadcast but can listen to the archive

Rookie

I do understand the difference between HDLs and other programming languages, through experience writing Verilog about 15 years ago.

Rookie

we are in the slice 3

Rookie

Had to reload page to get the audio player to load again... this didn't use to happen

Rookie

@phildani7... nope... just started a couple of minutes ago. welcome!

Rookie

Totally new have never worked with FPGA or SoCs

Rookie

I get the difference.

 

Manager

Ehllo everyone from INDIA

Rookie

@N9BDF hdl is a languaje of description of hardware

 

Rookie

hi just joined

did i miss much?

Rookie

I understand the delta between programming languages and configuring an FPGA

 

Rookie

Rel / Rad Engineer, working for defense company in NJ. I understand the difference.

Rookie

Worked with both types and think I understand them fairly well

Blogger

kinda confused... not so familiar.. yet :D

Rookie

Hello from Chicago in the states.

I do understand the difference between HDL's and typical programming languages...

Rookie

Yes, experience with verilog HDL

Rookie

I am a bit confused on the differences.

Rookie

@CoolNagesh::Read his book titled "Design Warriors guide to FPGA's" to understand everything about FPGA's.

 

Rookie

Understand completely.

Rookie

have worked a bit with both.

RELOAD your page to make sure you have the right audio

Rookie

Hi from Iasi, Romania

Rookie

Here in Colombia  (bucaramanga) we are at 23º

Rookie

It is a bit chilly here in Austin Texas as well

Ed Seymour

 

Rookie

Hello from Argentina

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Hello to all of you from around the world!

 

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Good evening all
from Italy 

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Hello from Brazil

 

Rookie

really cold and windy in the south of argentina

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Twenty twent twenty four hours to go ....

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Hello from Vietnam

Rookie

Morning all! Nice day here in San Jose too ;-)

 

Rookie

hello from Brazil! (very hot here, now)

 

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Good Morning everyone.

Rookie

Another calm night over here ;)

Rookie

@ Crusty, More time, yes & no...

I'm in Central Alaska and enjoying

my electronic retirement / continuing

education.

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good morning everyone, another beautiful day in Sunny San Deigo

 

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Hello everybody !!

 

Rookie

Hello from South Africa.

Hello Sir,Plaes say Something to me about FPGA,I am passionate about that...

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@ Rodney I am retired as well, but does it give you any more time to get on with your hobbies?

CEO

C Vs HDLs sonds interesting...

 

Rookie

Thanks @xcite,

I am already logged in and waiting for the live audio

 

 

Rookie

Hi From Crusty in tge South of England

CEO

@xcite.  If you are chatting, then you should be logged in.  You download the today's slide deck, and the live audio stream will apear above this window in 15 minutes.

 

Rookie

@xcite... there should be a log-in link in the upper right-hand corner of your browser on this page.

 

Rookie

how to login to the lecture. please anybody guide me

 

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I work as Associate Professor

 

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Hello from Scottsdale,AZ

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Good Morning from CNY.

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Hello from Huntsville, AL

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Hello somebody help me to login for the lecture. I am not getting any links on this page to view the lecture.

Rookie

I am an electrical engineer Telecommunications

Rookie


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