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Great presentation on FPGA for those just starting out...

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Finally got around to listening to this 5 day presentation.  Thanks again!  Whew...

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indeed very helpful this week. 

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Design west was classic "Max"!  Enjoyed reading about it on the Web!

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If it was easy, everyone would be doing it LOL

Temperature would seem to be a problem along with emissions could be a problem with 3D IC's.

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I have not done serdes yet.

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Thank you EE-Times and Thanks Max, for a great week of presentations.

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Not using and no plans to use Programmable analog.

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Thank you Max! Very good presentation.

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Would be nice to see next topics about FPGA noise immunity and radiation immunity.

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It seems as High Density Interconnect PCB at slide 17

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No evaluations on 3D IC technology

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In future, FPGA could get to the point of customisable product in form of personal device like programmable 'iPhone' of some sort.

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hello all from Edminton, Alberta

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future trends will be challenging

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soc could be alternate to complex PCBs

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Thanks Max; Great lecture

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Thanks Max, excellent information! I hope to learn more from your future sessions. 

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Excellent presentation all week long, be looking more, CA

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Thanks for the great series Max.

Very informative.

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Good morning all, from CA

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The gumbo, which book? got it, Third edition of BeBOP to the BOOLEAN BOOGIE...

What will Max the Magnificent come up with next?

Keep up the good work Max & Co.

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to everyone: Dr. Maxfield has a killer recipe for gumbo in Appendix J of his book - your mouth will water before you are halfway through reading it ;-)

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Signing off now .... Bye Byr - -hope everyne has a GREAT weekend......

Thanks to EVERYONE for attending and making thsi so much fun for me -- I hope to C U on All Programmable Planet

#Dave: Sure! are you interested?


What? Giving a guest lecture at the university in Durban, South Africa -- I'd love to (as long as they are paying for airface and hotel etc :-)  -- I've been to India and China and Japan and ... and a bunch of other places -- I gave a lecture at the University of Oslo in Norway in Feb of this year -- but I've never been to Africa

OK must go eat now! good night all! Tanks again Max!

@rganapathi: I'm reading B-to-the-B-B as we speak. Through about 1/3 of the book so far; I *really* like it!

Cool Beans -- you are my main man -- I'm glad you're enjoying it -- I love "tidbits of trivia" and "nuggets of knowledge" so I stuck a lot of things in there

I am a bit on the fringe here though. Most people here don't go to lengths I do to get info.

@Dave: I will think more about this.

There's a lot to think about -- one of the great things about these lectures is not that they teach you everything there is to know, but that they tell you about a lot of different things that are out there that make you think "I want to learn more about that"

Sure! are you interested?

I'm reading B-to-the-B-B as we speak. Through about 1/3 of the book so far; I *really* like it!

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@Dave: So you're in Durban South Africa ... I've never been to Africa -- maybe I'll get invited to give a guest lecture at the university there one day :-)

I will think more about this.

@Dave: Thats a good point Max.


Of course it is -- I made it (grin)

@Dave: NASA has used TMR since early Apollo missions


True -- very often they had three boards or even three complete systems

Also you have go higher than TMR -- in some cases they use five copies and vote amongst all five (not sure what that's called)

Thats a good point Max.

@Dave: TMR seems a bit drastic except for mission critical space devices


You don;t have to TMR the whole design -- you might just identify one critical functional block in the design and TMR that block, for example

NASA has used TMR since early Apollo missions

TMR seems a bit drastic except for mission critical space devices

@TomErb: Thanks so much fo rthe kind words -- if you do read Bebop to th eBookean Boogie I'd love to hear what you think (max.maxfield@umb.com)

@Dave: Doesn't rad hardening give enough protection in most cases?


Thsi is where things get complicated -- Rad-Hardening refers to doing things to the silicon -- lik eadding an epitaxial layer -- that helps prevent things like latchup

Creating rad-tolerant designs refers to the fact that radiation event swill occur and they will flop bits and suchlike, so creating your designs in such a way as to mitigate against these events

Great presentations, Max. And thx again to you, Brian, and EEtimes, for making it available. I think it's time I paid more attention to eetimes and programmable planet, and read the Bebop book to find out how things are done in the years since I graduated and got sidetracked by different types of work.

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Will do that. Thanks Max for a very informative series!

@Jnhing: Microsemi flash-based FPGAs (formerly Actel) have plenty experience with space radiation.  Check them out.


Microsemi/Actel also have a bunch of antifuse-based FPGAs (the RTAX family) .. .the big advantage of the SRAM FPGAs is their reprogramability ... also that you can get much higher capacities

you never know you might get unlucky

@Dave: I feel it everyday


Reminds me of the old joke -- "I feel like an old fool (but where are we going to find one at this time of the day?)"

You have to get probabilities before committing resources to avoiding an upset. Doesn't rad hardening give enough protection in most cases?

@cryptkicks: Keeping bopping to the boolean boogie

That's the spirit :-)

At the minute the devices in spartphones are custom SoCs creatied using ASIC techniques - -we are seeing smaller low-power FPGAs in thing slike digital cameras...

cosmic rays are detected by astrnomical image sensors at the rate of 1-10 hits/cm^2/min depending on altitude

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There's also the question as to id a particular radiation event matters or not. Suppose you have a space system that is taking pictures, storing them in on-chip memory, performing DSP on them, and shending them to Earth. If a radiation event causes a bit to flip in the middle of a 10megabit picture ... who really cares -- that will be filtered out by the DSP anyway -- so I probably woyuldn;t worry about protecing thsi memory

 

By comparison, if I have another block of on-chip memory that is storing my system flight parameters -- then I will use ECC, TMR, and memory scrubbing techniques to keep tha tdata pristine...

I'm not the person I used to be!

Keeping bopping to the boolean boogie

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So I'm kind of out of touch with current design and manufacturing techniques --  used to general purpose processor chips with programmable logic and memory. So this has been super helpful.

I'm curious: Are the SoCs in mainstream high-volume devices, like my smartphone, programmed FPGAs, or something more device-specific at that volume?

 

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Dave -- you are a mutant now.

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Well, I'm being paged .. gotta run.   Thanks again Max and Brian.  Looking forward to the next session, and perhaps the Design West conference    and thanks @jnhong ... I will.  'till next time or you can always message me ...

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I'm getting bombarding by cosmic rays and can't type propoerly!

Microsemi flash-based FPGAs (formerly Actel) have plenty experience with space radiation.  Check them out.

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@Dave: I take it sram fpga's are more susceptible that non-volatile programmable devives?

All FPGAs (actually any digital chip like an ASIC/SoC) has registers and memory cells tha tcan be affected by radiation (flip bits from 0 to 1 and vice versa) -- tyh ereason SRAM-based FPGAs are especially vunerable is that their confifuration cells can also be flipped.

There are ways aroudn thsi like using triple-more redundency (TMR) and detecting when a problem has occured and then using Dynamic Partial Reconfiguration (we talked about this yesterday) to reload that part of the device

@jnhong I know they are always present but its the likelyhood of them cuasing an upset thats the issue.

Mark -- check the ESC Design West website.  Plenty of the lectures are automatically free if you just attend the Expo.

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@Max ... Any chance of getting a geust lecture invite to "Design West in San Jose in April" ?   Might be good to see your presentation on Radiation fundamentals ....

 

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Max - can you bring a Geiger counter to the session?  People do not believe radiation and particles are always present.

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@aburgin: Thank YOU for your kind words

@Max: Have you been involved in any of the radiation testing of the Xilinx products? I know they have put a lot of effort into generating IPs that will mitigate and identify if an SET occurs

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@dave: Max, are there any numbers for probability of a rad event on the typical area of an fpga on Earth surface?

I'm sure there are, but I don;t have that Data to hand. One of the bloggers on All Programmable Planet is Adam Taylor in the UK -- he's working on using FPGAs in space -- he'll be giving a talk at Design West also -- he knows all ths istuff

@Max - Thank You for the effort and work you put into this lecture series!

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@jnhong: I plan to be at ESC in SJ

Cool Beans -- my session on Radiation will be one of the free "fundamentals" sessions -- if you see me wandering around (I'll be the one in a Hawiaan shirt) make sure to stop me ans say "Hi"

@Max ... yes ... I do ...  BTDT    lol.

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ok that sounds like something we should be concerned about then.

aburgin -- Xilinx and Altera have very good websites and training available.  Lattice and Microsemi not too shabby either.

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@mark: great pictorial representations

Thank you so much -- you wouldn't  believe how long it takes to create some of these in Visio

It sounds like Xilinx has become a lot more user friendly than it once was

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@Dave - 100% chance of getting a particle in its lifetime

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I take it sram fpga's are more susceptible that non-volatile programmable devives?

Max - yes I plan to be at ESC in SJ

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Max, are there any numbers for probability of a rad event on the typical area of an fpga on Earth surface?

Keep that topic feedback coming... you have some excellent suggestions! Thanks!

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Thanks Max.  Nice job.  I would like to see more detailed classes on specific parts.... Zynq 7000, in particular.

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Will anyone be attending Design West in San Jose in April next year?

Re partivles vs waves -- one problem is that at the quantum level particles tend to behave like waves

Thanks Max and Brian for the efforts to put together a interetsing set of days.  I'm hooked on the online educational benefits ...

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@all -- I agree with "jnhong" -- you can get some great free courses and training and materials at the vendor websites

Brian & Max thanks a bushel :)

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I have strong analog skills. What would be a great class would be a class to show example of how to take advantage of FPGA's in an all analog world. The mention of "Hampster" who created a transmitter to broadcast S-O-S is fascinnating to me. It leads directly into Direct Digital syntheses, which was starting to be a hot button at a former life.

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@luvac: Why are you referring to the 10 Gigabit Ethernet speed as 56 Gb/s ? Should it not be about 10 Gb/s ?

These are two seperate columns -- the left hand collumn is talking about different protocols -- th eright-hand column is showing how the speeds are increasing -- the columns are not related

lucavc -- draw a thick bold line between the two lists, up-and-down then you will understand

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@MaheshNarayan.Nadimpalli: (and I'm not going to typw tha tis more than once :-)  Re books, there are all sorts out there -- one I woudl suggest is written by Mike Field -- it's a free intro to VHDL -- it's based aroudn the low-cost Papilio FPGA board -- the best thing is tha tMike's book is free -- mike is known as "Hamster" -- if you go to www.AllProgrammablePlanet.com and search for "Hamster" you'll see a column tha tgives details about thsi book

@jnhong: yeah, but Max will be more entertaining. :-)

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Thank you Max and EETimes for another interesting session

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Slide 8.

Why are you referring to the 10 Gigabit Ethernet speed as 56 Gb/s ? Should it not be about 10 Gb/s ?

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You can get all the free workshops you want from the main vendor websites.  Today.  For Free.

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Agree with Aburgin.

"I'd like to see a "Hello World" workshop ... getting your first FPGA design working.  ... yes... definitely!"

 

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had to reload the page ... have to go through all the messages and am waiting for the last ones to be posted again.

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security implementation could also be a nice topic

 

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I agree, a "hello world" workshop would be really good

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+1 on the "hello world" workshop!

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Would like to see some real project examples involving FPGAs

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Bobo -- you need to tell your designers to include a debug/trace architecture into their designs, access by jtag or 2-3-4 wire protocol

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@Mark: Hahaha, it's all good

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I'd like to see a "Hello World" workshop ... getting your first FPGA design working.  ... yes... definitely!

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Thanks everyon efor the kind words. I will try to answer your questions, but some of the ones on radiation are a bit convoluted (the answers) -- what I wil ldo is write a coupel of columns on this next week or the week after and post them on www.AllProgrammablePlanet.com

Thanks! A lot info didn't pay attention before......good to know ;-)

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Thanks Max & Brian,Very informative!

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Thanks a lot MAX it was a great series of lectures.

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my bad ... Caps locks on ...

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Max and Brian, thank you

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It's been a great set of talks ... thanks very much!  I'd like to see a "Hello World" workshop ... getting your first FPGA design working.  Would have to be vendor specific but using introductory hardware is cheap.

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Thanks for sticking with us this week and especially for your patience with yesterday's technical problems!

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Hi Max can u suggest any good book FPGA other than what u have mentioned

 

where are slides located from prevoius sessions?

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Hardware and software comes together in FPGA land. Let the games begin !

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Good series, interesting discussion. Thanks Max, Brian, and you all.

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@WHYVEN ... OR IT COULD BE MY LIMITED DEFINITION OF RADIATION EFFECTS ...   THANKS

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FUTURE TOPICS: implementation of consumer and industrial applications using FPGAs and 3D ICs

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Troubleshooting circuits using FPGA's would be a great topic for me.

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Thank you MAX, for delivering s great lecture.

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Thanks Max !!!

Great Lecture.

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Max and Brain, thank you for this week presentaion. It was inforamtive and illuminating.

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yaa though i didnt attend it was useful I downloaded the slides

 

Thanks a lot MAX for the excellent lecture series

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Thank you for another great lecture Max!

Thank you Brian and EETimes for hosting

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Wow, Max ... once again your commentary brought on some interesting deiscussion !!!  THANKS !!!   Concur with bRIANS LAST COMMENT

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Thank you Max,

I've enjoyed the exposure into the world of FPGA's.

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@Mark: particle effects leading to SETs or SEUs would fall under the spectrum of "Radiation Effects" Perhaps its too broad of a spectrum

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@jnhong 100% probability of what?

@Max very good series of lectures many thanks EETimes university

CEO

Explain the difference between radiation and particle.

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Yes. 100% probability.

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@jnhong ... true, but I've viewed it more as a particle effect, not radiation ...

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Cypress give sea level RAD induced FIT rates for their SRAMs

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WHat happens if the voting circuit gets a SEP?

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I have simulated radation effect on 45nm and 60nm technology in the past

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Could be a higher probably of being struck by a passing comet!

Radiation and particle events have been happening to ICs since half-micron days.

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what is the natural event probability does anyone know?

never considered radition effects before ... but I can see that, as geomotries go even smaller, nearer to atomic size and/or manipulation ... it will become a concern.

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@Callaghan: do you want to be in a car or operating room when you get a rad event?

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Alpha particles are generated by the lead in the solder and the packaging itself.

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@Dave -- don't put your cell phone next to your Tritium gunsights.

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@Dave: At the SEE confrence they were showing test data that muons were causing upsets in 20nm technology

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I know rad hardening is essential for space apps but what is the probability of a rad event on Earth?

Cosmic Rays may be particles but they will slam into the upper atmosphere and generate a cascade of other particles and energetic gamma rays.

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When will we see DDR, Flash or MRAM dies alongside or atop a FPGA die?  Spartan3AN has boot flash atop the FPGA die.

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jnhong .... thasnk  lol

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 : abSOLUTELLY TRUE.

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going to listen for a bit ...

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@whyven... LOTS of scary possibilities... indeed.

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@Mark lol you are hardly the worst

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: Even I am interested in the question.

 

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(I really should check spelling ...)    temperature control will be the biggest hurdle to overcome for multi-die stack technology.

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Working in Rad engineering for 5 years now.  Atmospheric radiation is going to play a huge role in future designs as the technology shrinks... Imagine a pacemaker upseting because of an alpha partical

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Rad tollerant just wish DNA was

CEO

the best heat transfer (cooling) occurs through direct physical contact, next would be fluid flow, then air plow ...

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Amdahl and Cray tried micro-fluidic channels for cooling.  They didn't get far.

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@ Mark L Torrey: Agreed. But the ThetaJs are going to be horrid on these stacks.

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a former employer investigate many differnt approaches for 'heat sinking' ...

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I suppose the synthesis tool would take care of most of the work for the RTL designer when using a 3DIC. I would be interested how a 3DIC would impact the RTL design itself.

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temperature control is an age old problem even with single layer dies

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Can they "heatsink" the layers?

 

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I've designed up to the multi-chip module stage (ten years). I haven't worked with anything higher denstity.

Heat disapation is going to be a real issue with lots of stacked die. 

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great pictorial representations and explanations of the variations in use by many semiconductor companies, again .. . vertical integration through/across die to die ... biggest problem I could see would be cooling or heat control of typical (predictable) hot spots ...

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3d ic looks like the old jewelery enamling techniues, presumably you use different temperature solder?

CEO

3D ICs not yet, but very interesting.

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I understand that the gains from 3d chip stacking is not really worth the problems in getting the package fully ready for production. I expect other solutions to emerge soon.

SiP substrate can be multi-layer, like a micro-pcb.

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Advanatage of interpoesr?

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Yeah, what does Interposer do that SIP doesn't already do?

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What is the advantage of the interposer?

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Dice is the proper plural form of Die.  Thanks, Max.

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@ Sriharsha: Yes, the "package bumps" would the solder balls of a ball grid array.

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the FPGA's spartan can to work at velocities of Gbps?

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I used to call (slide 12) vertical integration ...

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Is package pumps are called BALL GRID ARRAY?

 

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Hey Max I am little curious about How could we implement Product Lifecycle Managment about the smart consumer and industrial applications using FPGAs and 3D ICs economically?

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slide 8: it's been said PCI express dominates usage?

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We have been using the niche market Serial-FPDP (sFPDP) but are attempting to migrate to PCIe over cable/fiber.

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10 GbE and Optical ... bt why 10GbE is liste as 56 Gb/s ?

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want to use serdes for connecting two links and link controllers

 

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No bias in my mind at this time :)

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How FPGAs and 3D ICs are extra smart in realtime from the traditional systems like

MCU/MPUs in terms of cost, design, consumer and industrial applications?

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agreed ... slide 7 ... T1 waveforms ..   seems on chip/off chip H.S. interconnect issues are very similar

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my experience with high speed interconnect is on chip ...

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Funny. Slide 7 looks like the old T1 waveforms. Good ideas keep getting recycled.

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Yes, we are using High Speed Serial Interconnects!

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Maybe LVDS isn't as fast as you're talking about - so far we haven't needed anything faster than that, and everything that's not display-related is even slower.

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Signal "seen" by receiver should be shifted right half of a bit time

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Starting to use serdes/lvds for high-bandwidth data acquisition, transfer, display.

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How about eliminating SKEW in the clock signal.?

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We are using Altera Stratix IV GT series that has got 11 Gb/s interfaces

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For those of you planning to use high-speed interconnect, what's the tipping point? A new application you're designing for or the technology's 'accessibility?"

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Not using high speed interconnect yet.

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Not now,maybe in the future.

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I'm working on some LVDS code today, as a matter of fact.  Using DisplayPort as well.

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No SERDES yet, but probsbly soon

 

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not using as of now but may be use in the future

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Use i2c / SPI for some things

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I plan to use high speed interconnects in future for my design

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@Sunny.song, the player should be visible just below the headline of this course near the top of this page.

 

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No plans to use serdes

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We probably will use some programmable analog and/or all-programmible stuff at some point but in agricultural machinery we're typically late adopeters because our stuff will be expected to run 25+ years - we wait until it's well proven and available in automotive-qualified packaging.

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@Sunny press play button at top of presenter's picture

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Analogue fabric is a great addition and will be why I want this technology. Heating controlls just to think on

CEO

Hardware simplification

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Hi there, is there any link to listen to the live audio?

First time user, thanks for help!

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In the near Future.

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Analog FPGA's - I'd love to ... but it was always too experimental

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Not at the present

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Using Cypress PSOC in one product

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not using any currently

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I am totally a digital guy.

But 

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Our designers here at work do.

 

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Future implementation

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good morning everyone

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Not using programmable analog

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What are some of the key design challenges you hope FPGAs might resolve for you in the coming years?

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Player is up and operational now.

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Hi all from brazil

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@Dave: The worlds finest minds...


LOL

Hello Max.

I am ready.

 

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Q: What do you call a man who isn't carrying a shovel?
A: Douglas

Q: What do you call a man with a wooden head?
A: Edwood

The worlds finest minds...

Q: What do you call a man with a wooden head?

Q: What do you call a man who isn't carrying a shovel?

What do you a call a man with a Cow sat on his head??

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Hello from Greece :)   

Q: What do you call a man carrying a shovel?

A: Doug    (you were right BruceMcLaren)

Good Morning everyone.

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@rganapathi: gullible? ;-)

Good One!!!

Q: What do you call a man with a seagull sitting on his head?

A: Cliff (grin)

good morning? I don't get it.

Hello from Birmingham (Alabama)

Wonder if this will be our last webinar before the end of the world in a couple of weeks?

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Q: Wha tdo you call a man carrying a shovel?

Q: What do you call a man with a seagull sitting on his head?

I saw a funny thing in this month's issue of the Reader's digest -- someone wrote in saying:

 

I bet when they first discovered the raddish everyone was like, "Let's name it Rad!" and one guy was all "Let's dial that back a bit."

 

Well, it made me laugh :-)

Yes, it rained yesterday. but sunny as can be this morning.

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@Max, as a video that might be ... interesting

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Not sure of temperature here but about 28C quite humid though after a lot of rain

@oldviking... did you folks get a front moving through there in the last 24 hours? My son in Tucson said it was raining and i thought that might have swept in from SoCal...

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Just for a laugh, I thought I'd give today's session in mime :-)

Beautiful morning in Costa Mesa, Southern California.

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Cloudy and 60F here in North Texas.

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Who's got the best weather today? In SF it's cloudy and in the low 50s..

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Hello everyone. Greetings from Durban, South Africa.

Hello from Coata Mesa, CA. 

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Good morning, everyone and welcome or welcome back! We shouldn't have a repeat of yesterday's technical problems (fingers crossed). We'll get started in 45 minutes.

 

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Howdy from Texas!

I'm listening to yesterday's seesion now. I had technical difficulties with it yesterday.

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Morning from Syracuse, home of the Orange (team, not the fruit)

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Good Mrng all ! India Nice weather and midnight !

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Good morning from Scottsdale

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Good Morning from San Jose, CA.

Partly Cloudy. It's 40°F now and a High of 52°F.

Could not Log in  yesterday. I just finished the Archived Part IV.

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Not being involved with design or programming, most of this week was just good information of the concepts to keep in mind and to perhaps get a bit more involved with.  

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Very informative week session

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Clive and EE Times, the slides look super.

Hope to see you all in a day or two.

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Dinh.Nguyen : you're a little early for Friday's seminar.

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