In a few minutes I will have to leave now to host the weekly live chat we have on All Programmable Planet (actually I'm already there -- I have multiple monitors and keyboards -- so I'm now in both chats -- my head hurts) -- it would be GREAT if you could join us -- just use this short-form link -- http://bit.ly/XXqPG0
@Dave: Does the CPLD have a permanent flash based configuration?
Ah, there was a question in there :-) The CPLD will almost certainly have a non-volatile configuration -- it might not b eFlash-based, it could be EEPROM (very similar) or fusible link or antifuse-based ... but these days probably Flash-based is a safe (or good) bet
@Dave: The internal config engine controls everything irrespective of the mode (serial/Parallel, Master/Slave, or JTAG) ... all of the config data passes through the config engine on its way into the confic cells
@erhk: Zynq will be able ro drive cheap LCD display?
I think with the Zynq you can drive just about anything. You can configure some of the programmable fabric to drive an HDMI display if you wish. One of the things folks are doing over on All Programmable Planet is creating their own soft cores to drive VGA displays -- I'm sure there will be soft cores available to drive cheap-and-cheerful LCDs
@bobo -- the problem is no different working with embedded microcontroller systems. If there is no trace and debug capability, no access to source code, you have very limited observations to make. Unless the debug was built-in, you are out of luck.
@dave: serial with FPGA as master means that the FPGHA is in charge of loading a serial bitstream from the outside world (usually a Flash memory chip). Parallel with FPGA as master is the same, but using a multi-bit-wide bus
Parallel with FPGA as slave might be using an external MCU to load the configuration data into the FPGA... etc
@Bobolicious: I think you have a big problem there -- if you don; tknow what's inside the design and have no way to access its registers, then you really are left just looking at the signals going in and coming out of the FPGA
@Throcko: Re accessing the archive -- I think you just come back to th emain course window listing all the sessions and click on the session you want -- if we've already done it then it's archived -- if we haven;t done it yet (like tomorrow's session) then it will send you a reminder...
I work with units that have many FPGA's used in the circuit designs. From a technicians perspective, not knowing exactly the designers programming concepts, is there a good way to go in and debug FPGA issues. I find the only way to look at inputs and outputs on a logic analyzer but would like to know whether there is a better way to troubleshoot FPGA circuits when often the design engineers are no longer around?
After this (at the top of th ehour) I'll be bouncing over to host the weekly live chat we have on All Programmable Planet -- it would be GREAT if you could join us -- just use this short-form link -- http://bit.ly/XXqPG0
Thanks Again for carrying on guys ... technical diffculties happen ... especially on the days when the schedule is a little more constrained. that's Murphy's Law ... right ?! Have bookmarked the AllProgrammablePlanet.com