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Counterfeiting:  In my current job, not such a big deal...

 

In my old job, it was a big deal - we were a DoD "trusted foundry"

 

Anti-tamper was a big deal.

Blogger

Looking forward to those radiation resistant discussions in next hour... 

Rookie

I have not used either of those design environments.

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look forward to the fridays presentation.

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Nice presentation.  bye all.

Rookie

Vivado is an amazing tool that does alot on its own.

Rookie

very big concern about counterfiting.  5

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I've done some basic design in FPGA's

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Thanks to advanced simulation tools ( a lot of which are free now) debugging has progressed tremendously.

 

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Debug takes more time as designs are more complicated - but the tools have evolved tremendously to help.

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No use of TotalRecall or GateRocket

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hello all from Edmonton, Alberta

Rookie

Missed the PART 4, becuase of Semester End Exam. But now I am going through that.

Feels good.

 

Rookie

Good Morning. I can't login yesterday. Maybe the class was Full and it won't let me in.

Rookie

Thanks Max and Brian; excellent presentation

Rookie

Glad the audio is still here for us slowpokes! Darn Work!

 

Rookie

Here's hoping no internet problems tomorrow.

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Thansk Tmka -- we're all chatting furiously over there -- look forward to seeing you there

Thanks for the link Max. I'll join gladly.

Rookie

I really appreciate your joing me here toda yand all the kind words -- tomorrow is going to be really good because we'll be covering all sorts of interestng things

In a few minutes I will have to leave now to host the weekly live chat we have on All Programmable Planet (actually I'm already there -- I have multiple monitors and keyboards -- so I'm now in both chats -- my head hurts) -- it would be GREAT if you could join us -- just use this short-form link -- http://bit.ly/XXqPG0

@Dave: Do CPLD's usually have non-volatile cofigurations?


Yes

@cryptkicks: The problem is to STOP me talking -- I coudl waffl eon fo rhours about almost anything (sometimes I even know what I'm talking about :-)

ok I think I'm getting this now. Thanks Max!

Do CPLD's usually have non-volatile cofigurations?

@Dave: Does the CPLD have a permanent flash based configuration?

Ah, there was a question in there :-)  The CPLD will almost certainly have a non-volatile configuration -- it might not b eFlash-based, it could be EEPROM (very similar) or fusible link or antifuse-based ... but these days probably Flash-based is a safe (or good) bet

Thanks Max , for the insights.

Rookie

@Dave: There is a CPLD on my target board that I think controls the SD flash config process.


Thanks for sharing :-)

Does the CPLD have a permanent flash based configuration?

@Dave: The internal config engine controls everything irrespective of the mode (serial/Parallel, Master/Slave, or JTAG) ... all of the config data passes through the config engine on its way into the confic cells

There is a CPLD on my target board that I think controls the SD flash config process.

@erhk: Zynq will be able ro drive cheap LCD display?

I think with the Zynq you can drive just about anything. You can configure some of the programmable fabric to drive an HDMI display if you wish. One of the things folks are doing over on All Programmable Planet is creating their own soft cores to drive VGA displays -- I'm sure there will be soft cores available to drive cheap-and-cheerful LCDs

I am currently configuring from JTAG but want to use SD flash config as well and for permanent power up config when the design is finalized.

Max, 

Currently, I am using Spartan-3 FPGA and Display Module but Display module is expensive. Is Zynq will be able ro drive cheap LCD display? 

Rookie

@bobo -- the problem is no different working with embedded microcontroller systems.  If there is no trace and debug capability, no access to source code, you have very limited observations to make.  Unless the debug was built-in, you are out of luck.

Rookie

ok so the FPGA internal config engine will control the whole config process when in master mode.

@dave: serial with FPGA as master means that the FPGHA is in charge of loading a serial bitstream from the outside world (usually a Flash memory chip). Parallel with FPGA as master is the same, but using a multi-bit-wide bus

Parallel with FPGA as slave might be using an external MCU to load the configuration data into the FPGA... etc

I cannot get access to the ppt... :( 

Rookie

Often cause me to pull my hair out.

Thanks

Rookie

@Dave: Master refers to the devuce that's in charge -- slave refers to the device that is controlled by the master.

ok maybe the master/slave just refers to the clock generator for data transfers?

@Bobolicious: I think you have a big problem there -- if you don; tknow what's inside the design and have no way to access its registers, then you really are left just looking at the signals going in and coming out of the FPGA

Thanks for the http://bit.ly/XXqPG0 short link, Max

Rookie

@Throcko: Re accessing the archive -- I think you just come back to th emain course window listing all the sessions and click on the session you want -- if we've already done it then it's archived -- if we haven;t done it yet (like tomorrow's session) then it will send you a reminder...

I work with units that have many FPGA's used in the circuit designs. From a technicians perspective, not knowing exactly the designers programming concepts, is there a good way to go in and debug FPGA issues. I find the only way to look at inputs and outputs on a logic analyzer but would like to know whether there is a better way to troubleshoot FPGA circuits when often the design engineers are no longer around?

Rookie

I would like to know more about slide 4 basic config modes. Eg. if not in JTAG only then you can still program from JTAG as well as serial/parallel AND what is meant by master and slave?

Thanks Max,

I will hear you tomorrow.

 

Rookie

Thanks Max.  After 28 years of designing, I'm amazed at how the basic concepts have stayed the same, and the tools have gotten so much better!

After this (at the top of th ehour) I'll be bouncing over to host the weekly live chat we have on All Programmable Planet -- it would be GREAT if you could join us -- just use this short-form link -- http://bit.ly/XXqPG0

What is the link to the All Programmable Planet chat with Max ?

Rookie

@Za: Thansk yo usom much - -the best we can hop eto do in these talks is introduce the fundamental concepts - -but knowing something is out there is 1/2 the battle

I too would like to see how to access the archive.

Rookie

Thanks Again for carrying on guys ...   technical diffculties happen ... especially on the days when the schedule is a little more constrained.   that's Murphy's Law ... right ?!   Have bookmarked the AllProgrammablePlanet.com 

Best To you

Rookie

Awesome, Max thank you for another great presentation.

Rookie

Max, 

Currently, I am using Spartan-3 FPGA and Display Module but Display module is expensive. Is Zynq will be able ro drive cheap LCD display? 

Rookie

@eexwd2 : download working for me.

Rookie

Please tell us how to access the archive for this session

 

Rookie

Can anyone download the ppt? It keeps giving me error messages...

Rookie

Has the talk finished? I cannot find the link to attend the course...

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@Pedro Salazar... we had technical problems on the live portion and came back on at Slide #16.

Rookie

finally server is up

Rookie

Our server had issues today also.

Rookie

I was unable to attend from the begining due to the techinal dificulty. i will have to check the archive  later.

Rookie

missed most of this session

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Yes me too - just logged on now

Rookie

It didn't work in St. Louis MO either until just now. I guess I'll just listen to the archive version (and skip the live chat). I'm happy that that's available. Thanks again, guys.

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I was not asking which slide.

Rookie

ok, i will watch the archived version

Rookie

now in the slice 18?

 

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Just now able to log in...interesting technical glitch.  I was trying the website every 2 or 3 minutes and on one of the tries I got a picture of a baby kitten (??????)

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technical and network issues going on here in Central Texas

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@boxerboxer... we should wrap the audio portion within 5-10 minutes and then dive into the chat session.

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Again, our apologies for our server problems this morning. This session will be archived immediately after the live portion, so you can catch up from the beginning of Max's presentation.

Rookie

Brian, what time did the presentation start, and what time do you expect it to finish, rougly?

Rookie

Well fially got here

 

CEO

I guess It's better to go through this lecture offline after it is archived. Wasn't able to join due to the technical problems.

Rookie

Holy cow!..... I've been tryig to get in for 40 minutes .... Only now, just got in!

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@moncho we're now on slide 16

Rookie

Which slide are we on?

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@crypticks... yes that was the case. The archive will be available immediately afterward so you can get caught up.

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wich slice coming now?

 

Rookie

Yeah, I couldn't post or do anything

Rookie

troubles with server/dns etc

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Good morning. Our apologies for the technical problems this morning!

Rookie

Web site just came up for me... been trying every minute or so since 11:58a ET.

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Thanks Max!  I am really learning a lot from the sessions.

Rookie

Morning from chilly Central New York

Rookie

Great slides, information and discussion.

Rookie

Moving from HDL to HLS, how can be the cost?

Rookie

Slides looking good Max.

Rookie


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