The asynch topic came up before and I did a little looking. The focus is on data transfers between registers and comparing the register contents with the bus to generate "I'm ready" can easily generate glitches. Many times there is a need to "remember" that an event has happened and a remember latch is used. Woops that glitch can cause metastability, now what? It goes back to the classic arbiter that generates responses based on priority. Two requests come in at nearly the same time with the lower priority first. The grant signal to the lower priority is generated, but shut off by the higher priority but the lower priority sometimes sees the ack and starts and the higher priority also starts -- BAD NEWS!
Then the thing about the clock tree. Everyone seems to be sold on pipelining because higher clock rates are achieved. THAT DOES NOT MEAN HIGHER PERFORMANCE! It usually means an extra register thrown in the path that merely adds to the signal delay. The IBM Stretch computer (1958) was a pipelined disaster and the Channel Controller (circa 1965) was the first time that circuit metastability was actually observed.