Nice article, Steve. And an interesting topic.
But, what about using processors (hard or soft) for that portion of your design which may be subject to updating? The update in that case is quite a bit less complex (load a new image into code memory). It seems to me that any designer considering a requirement for live in-field updates would certainly want to consider a processor-based design approach for such a block (instead of implementing that functionality in the FPGA logic). Of course, you'd still have to make sure you met your performance, cost, and power dissipation design requirements, but with the application -specific processor technologies that are out there now, this is tenable.
Blog Doing Math in FPGAs Tom Burke 14 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...