Also an EOT of 0.39nm with a dielectric thickness of 2.4nm requires an average dielectric constant of the gate stack of 25. This would require a crystalline dielectric without interfacial SiO2 layer. While this is not unheard of, it is typically not possible to achieve sufficient channel mobility in a gate stack like that.
A leakage current of 1e-12 A/cm² is physically impossible with an insulator thickness of 2.4nm. It would required a material with an unrealistically high band gap.
There appear to be factual mistakes in the article.
CYI-what are you talking about?
Being able to use a thinner EOT helps with gate control (short channel effects) as well as reducing gate leakage.
Granted, this article is not impressive with an EOT of 390A but I suggest you don't mislead others with a lopsided view on gate dielectrics.
While it is true that high-k materials will virtually eliminate gate leakage, the use of these materials will not significantly reduce subthreshold leakage which will continue to account for a significant percentage of a chip's total power consumption.
At 90nm, leakage power accounts for about 30% of a chip's total power and almost all of the leakage power is due to subthreshold leakage, as opposed to gate leakage.
At 65nm, over 50% of a chip's power is due to leakage and about 60-70% is due to subthreshold leakage.
At 45nm, gate leakage would have grown to overtake subthreshold leakage. With the use of high-k materials, the threat of gate leakage is tamed.
However, subthreshold leakage will continue to be a critical parametric yield-limiting factor at 45nm and beyond.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...