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pekon_
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re: Verilog versus VHDL (which is best?)
pekon_   7/26/2011 8:23:10 AM
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I do not agree with you.. 1) Verilog is good, b'coz its less easy to learn and type. After all digital design is just one aspect of whole electronic-system. you would certainly not like to spend your whole life doing one thing, and same thing.. (so better learn fast, work fast, and move on) 2) Being strongly typed, VHDL catches many errors during compilation itself. However, these are mostly 'Lint' errors, which a experienced designer can catch easily on his code review. Also, verilog tools nowadays are intelligent enough to report same. VHDL was good in early 80-90s. But now surely Verilog. You havn't seen Verilog in big companies, bcoz either new IP have old VHDL engines in them OR, most digital designers are from VHDL era.. [pekon]

pekon_
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re: Verilog versus VHDL (which is best?)
pekon_   7/26/2011 8:14:43 AM
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very nicely compared.. [pekon]

clematis
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re: Verilog versus VHDL (which is best?)
clematis   7/25/2011 7:15:24 PM
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I've heard it said, at least in the USA: VHDL on the east coast, Verilog on the west coast.

James.Brady_0623
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re: Verilog versus VHDL (which is best?)
James.Brady_0623   7/25/2011 6:53:08 PM
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Seems like VHDL is used a lot in England and on East Coast, and Verilog more on West coast. I am a C firmware programmer for 25 years, and have been using both VHDL and Verilog the last few years. I prefer VHDL because it has stronger type checking and catches bad code more often. Also, VHDL is also more consistent with signal processing using signed types. Signed math in Verilog seems like afterthought, and it lets you get away with doing error prone stuff like adding a signed to an unsigned. And finally VHDL feels "higher level". Verilog uses "wires" and "regs" which seems pretty close to hardware, although some may prefer that. Jim

rays14
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re: Verilog versus VHDL (which is best?)
rays14   9/12/2010 7:07:26 AM
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Yes. Surprisingly lot of people use vhdl. I was told in school as recently as 2006 that vhdl is "dead". Not so in the places I work at. It is alive and well and yes in the U.S. My work often involves lot of DSP and controls. And the projects have varied in size from a one man show (myself) with about 1500 lines of vhdl to about a 100000 lines of code with multiple engineers on it. Most engineers come with verilog background just like me. I do keep up with verilog in my garage projects but there are significant deficiencies. Maybe systemverilog fixes those deficiencies. The one big issue I have with verilog is no parameter arrays and no port arrays. After using vhdl I find making reusable code in verilog is a problem because there are no uncontrained ports, no data types, no attributes such as length, high, low, range etc. which are very nice to have to write generic modules. In vhdl just define a port as unconstrained and then attach to any module that provides an actual parameter and thats it. This I found a huge advantage when I was designing an N-tap fir filter recently. I just designed a generic fir-filter and could scale the damn thing from a 5 tap filter to a 50 tap filter by just providing an array of impulse-responses. The fir-filter was generated based on the size of the impulse-response array. Most of this is just bad press from people who have been told my universities that vhdl is bad. Nobody knows why it is bad. I have used both languages and find vhdl to be more powerful. Haven't used systemverilog so cannot comment on it. All the advantages I have seen on systemverilog(from the little I know about it), vhdl already has them. Somebody said that in verilog there is a @* and vhdl has nothing like that .. baloney .. vhdl has an 'all' that already does the same thing.

rays14
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re: Verilog versus VHDL (which is best?)
rays14   9/12/2010 7:06:39 AM
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I do agree that aerospace and defense use vhdl but that is the industry I want to be in because those jobs are not going to be shipped to a foreign country. Also the monies involved in the industrial military complex is far greater than any other industry in the world. We have the money and we will support vhdl. And unlike popular belief the projects I have worked on are all brand spanking new. Not legacy as everyone likes to believe. Writing code in verilog is faster. Good for competition. No doubt. But when your family and children are on an airplane I doubt any of you will be so excited to know that your competition winning code is flying the jet. Trust me if your code bring the jet down heads are going to roll. When the US military is fighting a war against people ready to die I doubt the same will be true in that case too. Our weapon systems are the finest in the world and there is a reason for it. DISCIPLINED engineering, world class tools and no tolerance for hacking. Take your time to build a solid system.

rays14
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re: Verilog versus VHDL (which is best?)
rays14   9/12/2010 7:05:30 AM
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Yes. Surprisingly lot of people use vhdl. I was told in school as recently as 2006 that vhdl is "dead". Not so in the places I work at. It is alive and well and yes in the U.S. My work often involves lot of DSP and controls. And the projects have varied in size from a one man show (myself) with about 1500 lines of vhdl to about a 100000 lines of code with multiple engineers on it. Most engineers come with verilog background just like me. I do keep up with verilog in my garage projects but there are significant deficiencies. Maybe systemverilog fixes those deficiencies. The one big issue I have with verilog is no parameter arrays and no port arrays. After using vhdl I find making reusable code in verilog is a problem because there are no uncontrained ports, no data types, no attributes such as length, high, low, range etc. which are very nice to have to write generic modules. In vhdl just define a port as unconstrained and then attach to any module that provides an actual parameter and thats it. This I found a huge advantage when I was designing an N-tap fir filter recently. I just designed a generic fir-filter and could scale the damn thing from a 5 tap filter to a 50 tap filter by just providing an array of impulse-responses. The fir-filter was generated based on the size of the impulse-response array. Most of this is just bad press from people who have been told my universities that vhdl is bad. Nobody knows why it is bad. I have used both languages and find vhdl to be more powerful. Haven't used systemverilog so cannot comment on it. All the advantages I have seen on systemverilog(from the little I know about it), vhdl already has them. Somebody said that in verilog there is a @* and vhdl has nothing like that .. baloney .. vhdl has an 'all' that already does the same thing.

old account Frank Eory
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re: Verilog versus VHDL (which is best?)
old account Frank Eory   9/7/2010 10:34:57 PM
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Wow, the differences between ASIC & FPGA go far beyond synthesis and P&R tools. People still use VHDL??? I actually learned VHDL first, and back in the '90s the battle between VHDL & Verilog was something like a religious war. But as an ASIC designer working in the U.S., I had no choice but to learn Verilog, and I haven't seen a line of VHDL code in probably 15 years. Defense contractors here still use VHDL -- it is often a requirement, which is not surprising since VHDL was invented by the U.S. DoD. Europeans seem to still like it too. But if you are doing ASIC work, your standard cell library and therefore your final netlist are going to be in Verilog, so you can choose to go with both languages, or just standardize on Verilog all the way. I remember when John Cooley used to do his Verilog vs. VHDL coding shoot-offs at DesignCon back in the '90s. I always felt sorry for the VHDL guys. They had to write 3x as much code to do the same function, and since it was a timed competition, they never had a chance!

rays14
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re: Verilog versus VHDL (which is best?)
rays14   9/7/2010 8:49:34 PM
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All companies I have worked for has standardised on VHDL. Did verilog in school for digital logic class. In proffesion all places I worked at in the US does VHDL. Lot more advantages in VHDL over Verilog in terms of code reuse, parameterization, packages etc. Also VHDL has better hardware design expressive power than verilog. Also it accepted by engineering comunity more than software developers pretending to be hardware engineers.

alexzabr
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re: Verilog versus VHDL (which is best?)
alexzabr   8/21/2008 7:54:59 AM
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Well, I cannot boast by a broad FPGA/ASIC design experience, got into FPGA/CPLD field recently and made up my mind for VHDL. I indeed like strong typing, prepared to invest more in study to gain a strong understanding and be in control of the process and for that VHDL does sound to be the tool. Having said that, previously I used to work in quite renown in digital camera/DVD/DTV SOIC ASIC design company and there ASIC design/engineering is built around Verilog of course. What I noticed from there is that often a pure hardware concepts got lost or diffused being masked by Verilog easiness and sometimes I indeed encounter software-titled engineers writing Verilog quite promptly, but often lacking a pure hardware understanding behind that. Now, working with a small company where I'm happened to be "the hardware guy" I make up the policy of hardware approach including design approaches and I went with VHDL. Of course, YMMV..

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