I would say to new students and newbies, learn BOTH syntax and merits of VHDL & Verilog languages.
Then be prepared to excel in either one been used by the project at hand.
I seen it many times, a project is launched using either verilog or VHDL, and members have to merge IP form the opposite language, and learn sideeffects in compliler and simulation applications. There are many ways to skin a cat, so use the tool that is appropiate for the job at the time of need.
University I went to swears by Verilog. Yet the big defense company sitting next door to it swears by VHDL. So I know both and can move from one to the other without a problem. However, proffesionally it has all been VHDL for me. If I need to do Verilog I have to move to California :(. But no Verilog in my town.
Not really. From an academic point of view, VHDL is a better teaching language. Professors might choose Verilog for other reasons: company sponsorship, prevailing language in their research labs etc. but from a purely academic point of view, I doubt many would "choose" Verilog in teaching.
I would say start with VHDL and then switch to Verilog. VHDL is a well structured strongly-typed language with a strong declarative ethos. It can't be easily confused with other software languages e.g. C, which is a good thing for a newbie. Its verbose nature means however that it's more suitable for small designs. So when you get the HDL concept, switch to Verilog. It's a much more elegant language; and provided you know what you are doing, it should make you more productive. Also SystemVerilog is major extension of Verilog which allows for complete system design and verification within the same language. It is also widely used by big design companies for modelling, and in time for synthesis too. All in all, ignore System/Verilog at your own peril....
It's interesting that this thread has been resurrected. Almost a year after my last post here, I still ask, where are all these VHDL coders? Defense, aerospace, Europe, Israel...and let's don't forget FPGA designers. Ok, I get it.
As a DSP guy, I really appreciate some of the features of VHDL over Verilog. But when all is said and done, any decent designer should be able to adapt to whichever language his employer prefers. But if you're doing a real chip design, at some point (synthesis) you're going to deal with the foundry's std cell libraries that are Verilog.
So the question really becomes, do you prefer to do your design in a mixed language VHDL + Verilog environment, or just in Verilog from top to bottom?
I'm surprised at UdaraW's comment that the academic community prefers to teach Verilog. I would've thought just the opposite, since VHDL seems to me to be much more "academically pure". But industry tends to follow the herd (i.e., whatever is more widely used and thus cheapest), which would clearly be Verilog.
Maybe it's another case of VHS vs. Betamax. Everybody knows that Betamax was a technically superior videotape standard, but VHS won anyway...
Lot of companies use VHDL. All the defense companies use it. Aerospace companies use it. I worked for defense, aerospace and nasa. So that is not a true statement that only NASA uses VHDL. That sounds typically like what a prof. would say. Proffesors are not a good source of real-world information. Industry is. Having said that, if you prefer verilog then use it. There are others who prefer VHDL. I don't see any diffucutly doing vector shift in either language because I use both. My garage projects are in verilog and work projects are in VHDL.
Don't do that. If the proffessor wants you to use verilog then use it. Trust me proffesors don't have much industry experience. On an average they have 3 months of industry experience as an intern. They do have phd's and are very sensitive about it. They can make your life miserable. So just get the project done in Verilog. These are just HDLs. Once you know how to design the language is not going to make any difference. Its personal prefference. I have designed hardware using both languages. Makes no difference. This is really a dumb thread because there will be a new language tomorrow and everybody will jump on that bandwagon.