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tb1
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re: Viewpoint: Standard FPGA-based emulation will prevail
tb1   2/25/2009 7:58:02 PM
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"it will be possible to produce a 100-million ASIC gate emulator with 16 FPGAs for less than $50,000. This machine will run at approximately 10 MHz." People sometimes forget what an emulator is for. It is not just to emulate the design. If you just want to run your chip then just build it. It will run faster than -any- emulator, and it is much easier to setup. People want emulators to test and debug their designs--faster than is possible with simulators. It is not just how fast you can run the emulation, but how fast you can compile it, how quickly you can debug any problems, and then how fast you can re-compile it again after you find the fix. If it takes days to compile, then hours or days of running for a bug to show itself, you can't afford the time to add probes, recompile and run again. Many non-FPGA based emulators compile multiple millions of gates in hours, and when running can record the state of every single node in a system around a trigger point. So when the bug occurs, you can don't have to add probes and re-run; you can trace the nets back to the problem and immediately see the waveforms. If you think of it as a design debugger instead of an emulator there's a better chance you'll look for the right features that will get you to your finished working chip faster.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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