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mcgrathdylan
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re: Intel, Numonyx claim phase-change memory milestone
mcgrathdylan   10/29/2009 12:58:15 AM
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Well, there's the big question, right? I am going to guess that ECD Fan isn't voting for PCM. I'd love to see what others think.

toom_tabard
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re: Intel, Numonyx claim phase-change memory milestone
toom_tabard   10/29/2009 12:36:35 AM
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That 3D cost model I referred to was in May 2009 IEEE Trans Semi Manufacturing. It showed that monolithic 3D Flash, besides being inevitable, has an optimum in the number of added device layers. The great question that remains is: which 3D Flash alternative will prevail ?

toom_tabard
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re: Intel, Numonyx claim phase-change memory milestone
toom_tabard   10/28/2009 9:18:23 PM
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Interesting work from Numonyx. I agree with "ECD Fan" - Samsung have already stacked both floating gate and TANOS versions of NAND using their epitaxial silicon growth technique. The floating gate version has the same scalability issues as 2D NAND while TANOS has read-pass disturb issues (among others). It will be interesting to see if Numonyx has solved the problems of integrating a high current carrying non-linear element (i.e. a stacked diode) with the PCM material. The question of cost in such approaches has been solved - see May's (2209) edition of IEEE Trans on Semi. Manufacturing. In any case, their approach as presented in the EE Times article sounds sort of similar to SanDisk's 3D approach (http://microlab.berkeley.edu/text/seminars/MonolithicMem.pdf).

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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