If I remember correctly, one of the major issues with the reduced features is the wafer yield due to bad cells in arrays. One way that was used (not sure if everyone does this now) was to provide redundant rows/arrays and at die test blow fuses to switch to good from bad arrays. The thing about DRAM technology was not just that it drove the process but it lead the way to maturing of the process due to the large volumes that DRAMs entailed. I look forward to the next leap in technology (what ever that is).
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.