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KarlS
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re: What's Your Take on Tabula?
KarlS   10/29/2010 3:53:16 PM
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Yesterday there was an announcement that the Tabula CTO is they keynote for a seminar next month. Topic is a new cpu architecture that eliminates von Neumann bottlenecks. No doubt it will be based on this approach. I am guessing it may use more than one config so that one executes while the next loads. With chip densities available it is hard to see the advantage of "paging". Any high level language has only a handful of statements to control assignments and looping. I just put all the variables in a multi-port ram, pop out 2 operands do the operation, repeat or write result, and go on to the next statement. Using multiple rams with overlapped access is the way and all the complexity and overhead of multi-core/pipelining/branch prediction kind of stuff just goes away. Just imagine a bug where the wrong page gets loaded in this scheme. By the way, I also registered at the Tabula website and got very little info. Looks like another case of doing something because it CAN be done, rather than it SHOULD be done.

fpgachip
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re: What's Your Take on Tabula?
fpgachip   9/3/2010 4:06:34 AM
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No big deal really. Tabula's space time technology is nothing more than serially reading out pages of a config ram. Consider a N x M array of ram bits. These bits configure a basic LUT just like Xilinx or Altera config rams. Now imagine 8 of these N x M ram arrays grouped together. Normally to read out 8 different pages require a 3 bit select. But obviously you can also do it with 8 serial decoded page select bits. Having 8 serial bits means a 8 bit page select register which can shift at multi Ghz speed to select each N x M page in sequential order. Easy when it's just a 8 bit shift register. So each of the 8 pages are sequentially read out of the config ram to reconfig the LUT to do a different function. Now obviously you need some FFs to hold the value or context of the previous page of config ram while you shift to the next one. Of course, the big trick is how to map a Verilog or HDL design into sequential paged logic. But the solution is not that hard if you think about it. I'll leave it to the student. email me when you think you have the answer.

pjduncan
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re: What's Your Take on Tabula?
pjduncan   3/8/2010 7:56:23 PM
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If this technology truly can bring the effective system clock rates significantly above what is supported by today's FPGAs (such as reaching 400 - 500MHz) they might be very popular as a validation platform. It would seem this approach is going to have a significant power penalty compared with ASICs in addition to die cost disadvantage. Seems worthy of a closer look when they release details.

chinookpass
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re: What's Your Take on Tabula?
chinookpass   3/4/2010 4:07:32 PM
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Two main questions. Do area and power tradeoffs equal a win? What portion of standard designs map well into this structure? This does not appear to be real-time configuration that pabitt is talking about since it is on a per cell basis and it is cyclical in nature over 8 cycles.

pabitt
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re: What's Your Take on Tabula?
pabitt   3/4/2010 3:54:54 PM
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This technology does not lend itself to real time streaming communications. A modem per say or any networking device that has data constantly being streamed to it may not be able to halt the data and reconfigure for the next function without valuable data being dropped. If the processing was fast enough you could theoretically get through all of it in time before the next bit of data arriving at the physical port but to meet line rates of 10Gbps or greater I don't see this happening. Maybe for smaller more processing intense applications this technology has an advantage. Seems like more of a niche product than a general main stream technology. Not to mention that the giants (Xilinx & Altera) have been working on real time reconfiguration for a while. I would imagine if the bulk of the market were really interested in this technology that it would have been made a reality before now.

clematis
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re: What's Your Take on Tabula?
clematis   3/4/2010 3:41:29 PM
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Ah, busted again! My browser seemed stuck when I hit "send" - so I hit it again. Glad I wasn't purchasing something!

mcgrathdylan
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re: What's Your Take on Tabula?
mcgrathdylan   3/4/2010 3:35:30 PM
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Thanks for the great comments. These is the kind of detailed stuff we needed. Anyone else want to weigh in here? Clematis, I appreciate your effort to make this forum more active by submitting twice, but I'm afraid people will see right through that strategy. :)

clematis
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re: What's Your Take on Tabula?
clematis   3/4/2010 3:16:18 PM
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I went to the Tabula website to learn more about the chips. It seems that if the chip performs as advertised it will be able to effectively operate in the 1 GHz range. However there is little detailed info for an engineer wishing to see the nitty gritty. They make you register to obtain any data - big mistake, they should be offering copious and easy downloads for their product info. I did register thinking I would quickly get a return email allowing me to access more info. I'm still waiting. The website seems geared toward investors, not engineers. If they want engineers to design in their chips they will have to become more engineer friendly. But the info I got about the chips seems really cool. John

clematis
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re: What's Your Take on Tabula?
clematis   3/4/2010 3:16:07 PM
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I went to the Tabula website to learn more about the chips. It seems that if the chip performs as advertised it will be able to effectively operate in the 1 GHz range. However there is little detailed info for an engineer wishing to see the nitty gritty. They make you register to obtain any data - big mistake, they should be offering copious and easy downloads for their product info. I did register thinking I would quickly get a return email allowing me to access more info. I'm still waiting. The website seems geared toward investors, not engineers. If they want engineers to design in their chips they will have to become more engineer friendly. But the info I got about the chips seems really cool. John

amiga89
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re: What's Your Take on Tabula?
amiga89   3/4/2010 3:01:30 PM
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There is not that much actual information available on the technology, but here goes. Assumption. The configuration information is set up in a circular shift register, so in effect n (8?) circuits running at less than clock divide by n Mhz can run as long as they don't need to interact. Think of it as hyperthreading for logic. From there it gets complicated. I worked on the same sort of thing used for simulation over 10 years ago, bottom line is designing for these devices is tough if you want to take advantage of the density multiplication. Given that FPGAs have a density disadvantage over ASICs of at least 20 to 1 anything that cuts that down to under 5 to 1 really moves the point when it is worthwhile to go to ASIC. Assume less than 2T (transistors) for each config bit you get to reuse the routing fabric and any hard logic for very low area cost. I am going to assume that the tools are going to be problematic in the beginning. The make or brake here will be the cost of the devices. If these devices are cheap enough so they can compete with ASIC and then the design wins will come. The path will become FPGA for prototype, Time Div Logic Arrays for medium production and ASIC only if there is absolutely no alternative or massive volume. If the cost advantage is great enough, the money available will quickly generate FPGA to TDLA conversion engineers and service bureaus who are willing to endure the pain of a new tool chain. BUT we do not know much about the IO, the power profile or the cost and historically configurable logic manufacturers have not been very good partners for high volume, preferring to get much of their profit from the high end. The game is afoot..

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