The problem with CPU-inside-FPGA approach, at least with my experience using MicroBlaze in Spartan 3A, is that there is not enough block RAM in the FPGA to hold a typical embedded app. The RAM must hold both code and data, and 45 Kbytes in the 700A part is just not that much.
So you have to use an external DRAM. And the DRAM controller IP core is complex, for example the datasheet for the Xilinx mpmc core is over 200 pages in length. So you will have a lot of learning to do!
Another problem with CPU-inside-FPGA approach ...when you include cost of external DRAM, and needing to use a larger FPGA to hold CPU .... it is no cheaper than separate CPU and FPGA approach. CPUs like Cortex M3 are very low cost.