It's lovely to see such extended treatment of JFET amplifiers. How many other people out there get the same rather wistful feeling that I do, though? The big semiconductor manufacturers have culled their JFET ranges to extinction, leaving the market mostly to specialist vendors such as Linear Systems. Depletion-mode FETs have the wonderful characteristic of being conducting when no gate potential is applied; this behaviour is really hard to replicate otherhow. There are a few depletion MOS devices out there; single-source and in quite large packages. I feel rather sad that the JFET is slowly fading from our design consciousness. What do you think?
You need to establish a base bias suffficent to operate the lower device in/near the pinchoff region, i.e., where its output impedance is reasonably high. You do not want the base voltage to (partially) track with the circuit output voltage---this tends to defeat the purpose of the cascade, which is to minimize the voltage swing on the drain of the input device, thus reducing drain-gate capacitance multiplication ("Miller effect"). In some cases it is advantageous to derive the base voltage from a sample of the actual circuit input voltage, reducing the effective FET input capacitance further---however, this will result in negative input impedance at high frequencies and potential instabilities.
I would like to explore the cascode configuration of fig. 9.15 but with Q2 replaced with a BJT. My question concerns biasing of Q2 when it is a BJT in a common base configuration. Does it matter if the base biasing resistor is connected directly to Vcc or the bottom of R2 where the Output is tapped? How do both arrangements affect the overall cascode circuit gain?
Blog Doing Math in FPGAs Tom Burke 18 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...