The current is not the 200MA/cm2 in the 16nm feature. It is the 600uA. I assume they meaured roughly 600uA and devide by 16nm x 16nm area to get to 200MA/cm2. Reverse thinking: if you bundle in parallel a bunch of those 16nm features to form an array that has an area of 1cm2, than you will need 200 MA to program them all together.
So in other words, the concern in the article is that 600uA is large for 16nm node. Therefore the viability of PCM for memory is in question!
OK now I get it. Thanks for the clarification.
It's still hard to see where all the current will come through. There's only so much metal in the stack and you still have contacts and vias which not support such current densities. It's not just at the transistor/channel level where the current density issues will occur.
A/cm2 unit represents current density which is standard in semiconductor devices. For instance, in the 200 MA/cm2 and 16nm node/size one would get a current of 600um for that given node (assuming a square 16x16 nm2), which cannot be easy to visualyze if compared to the "current" of another size.
To J N Hong and Worker Bee
I have quoted directly from the abstract of the Numonyx paper, as published by the IRPS organization. Readers can follow the link to http://irps.org and then navigate to find the program and the paper at http://irps.org/conf-info/Thursday_Program.pdf.
Please bear in mind that the authors are dicussing current density and have chosen to use units of amperes per square centimeter, which is quite usual. The conducting channels are of nanometer dimensions.
My understanding is that current densities of 10^5, 10^6 and 10^7 A/cm^2 are quite usual in microelectronic structures. Clearly 2 x 10^8 A/cm^2 is extreme but that is the point of the paper.
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