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KarlS
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re: Design challenges in DRL
KarlS   5/21/2010 3:14:03 PM
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Before HDL was invented control and data flow were separate in computers. The most concise way to describe a design is with Boolean Algebra because controls are implemented in and/or/not blocks and data flow is add/sub/mpy/dvd/and/or/xor. So the separation is desirable. The part that is not not so obvious is the advantage of focusing on the function block and connecting the function to the register. It is another way to do pipe-lining so the gating selects the operands rather than moving the data into the next register. There must be enough registers to hold all the operands and each function combines 2 operands into 1 result which is then used in the next function so the data is still moved. As usual this focuses on an operation that can be pipe-lined, not the decision logic where the most cycles are consumed.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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