Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
KarlS
User Rank
Author
re: Reduce parallel programming pain with dataflow languages
KarlS   6/28/2010 5:36:28 PM
NO RATINGS
In figure 3, what is the advantage of pipelining over simply having each core run on separate data streams? DKC: What makes RTL synchronous? HDL blocks are typically edge triggered and typically use a clock edge so that only 1 signal is involved, otherwise bad things called glitches occur when detecting the "edge" of combinatorial logic. Asynchronous data transfers require deskew of the bits which requires a time delay to wait for the slow bit and delays are not well controlled in silicon. How do you expect the FSM state chabges to be triggered? HDL is compiled to RTL before anything useful happens, so if the latest silicon does not handle RTL it is useless.

DKC
User Rank
Author
re: Reduce parallel programming pain with dataflow languages
DKC   6/28/2010 4:34:35 PM
NO RATINGS
You can also just add the language features of HDLs (Verilog/VHDL) to (say) C++, and get a not-so-new language that handles data-flow & event-driven programming - http://parallel.cc The main issue is that neither shared memory or synchronous (RTL) design styles work efficiently on the latest Silicon. Going forward hardware design and software design are going to start looking very similar - asynchronous communication, FSMs, and lots of threads. http://www.linkedin.com/in/kevcameron

<<   <   Page 2 / 2


Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
Special Video Section
5G LTE is on the way. These systems will require more ...
Protecting sensitive electronic circuitry from voltage ...
09:45
Watch as a web server authenticates or rejects a water ...
Protecting sensitive electronic circuitry from voltage ...
Watch as a web server authenticates or rejects a water ...
Protecting sensitive electronic circuitry from voltage ...
Power can be a gating factor in success or failure of ...
Get to market faster and connect your next product to the ...
00:44
See how microQSFP is setting a new standard for tomorrow’s ...
The LTC3649 step-down regulator combines key features of a ...
Once the base layer of a design has been taped out, making ...
In this short video we show an LED light demo to ...
The LTC2380-24 is a versatile 24-bit SAR ADC that combines ...
In this short video we show an LED light demo to ...
02:46
Wireless Power enables applications where it is difficult ...
07:41
LEDs are being used in current luxury model automotive ...
With design sizes expected to increase by 5X through 2020, ...
01:48
Linear Technology’s LT8330 and LT8331, two Low Quiescent ...
The quality and reliability of Mill-Max's two-piece ...