I agree with winux.. It is unlikely that high volume manufacturers like Samsung or Intel would like to adopt a standard and share the pie; they will like continue having the full cake.
I think 3-D integration has potential for integrating heterogenous entities such as MEMS, speciality analog etc. Such products have fragmented and often low volume market, so large chip manufactures have little motivation in pursuing.
Hence the drive for this technology and standard is likely to come from small companies.
When considering 3D chip stack for SiP, yes the heat dissipation
is a kind of addition of the individual heat of each of the dies.
That addition is not true when considering 3D-ICs consisting
of one design where the floor-planning, partitioning, and place & route
has been done in 3D.
The gain on the power dissipation is of a two order of magnitude than
for a same design implemented in 2D.
Total wiring length and gate sizing are drastically reduced involving
less power consumption, while the performance increases significantly.
It's like for buildings, they are not made by simply stacking individuals houses !
I really think that in 3D integration the first issue to have a standard emerging is not technical. We can rely on the creativity of engineers to find an elegant solution to the various technical problems attached to 3D technology.
For me the real first issue is the business model of this apporach. Let's take for instance the wide IO connection. Why samsung should push for a standard in order to have a chance to loose part of the business while they can get the whole cake in providing DRAM and the digital SOC above or underneath the memory? This issue is the same in other cases. What is the share of revenue and cost between dies coming from different vendors? How is the cost of bad dies/testing shared ?
I personnaly believe that without a clear known and established biz model, the emerging of standards in 3D will be quite hard even if every body is convinced that it is needed.
Good points, Bob. One of the big issues is how to set standards when there are so many ways to do stacking. But I think the benefits are clear and people like Qualcomm are "hot" on the tech, if you will.
I wasn't able to post a picture of a silicon interposer approach Xilinx talked about. It seats die side-by-side on an interconnect layer--perhaps addressing heat.
It's not hard to see the drive to 3-D chips--what's even more interesting would be so see the packaging, and in particular, the cooling techniques that will have to be applied. Planar devices sometimes wind up in large packages suitable for frying an egg: at least, a robin's egg. A 3-D chip stack has the potential to have plenty additional heat to dissipate. Should the standard cover package form factors? Or even set out to talk about heat rejection?
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.