nSys offers products and services for accelerating designs while lowering costs.
nSys is perhaps the only company in the world focused on Verification. Customers are appreciating the option of getting all their VIPs from a single source without having to struggle with different licensing terms, agreements, APIs, simulator versions and training for every VIP.
Most customers also appreciate the flexibility that we offer. You can get annual licenses, Source code licenses and even Unlimited licenses.
We would like to understand how we can be of help in your Verification effort. We would also like to ensure that you do not ever have to develop a VIP and can get proven ones when you need them.
Yes, it is all about ROI, which management will understand. Jasper’s approach to formal verification is that there must be a positive return on investment from the very first project. We also provide deep applications support that brings verification engineers, and design engineers, up to speed fast without schedule impact. Using formal justifies the cost and time you mention in many ways, especially finding critical and corner-case bugs which cannot be detected in simulation. Jasper's formal solution can exhaustively verify all design scenarios without any input stimulus or a testbench and can save weeks, if not months of testbench development and random simulation effort, leading to increased confidence in the overall verification process. Jasper is also used across a spectrum of applications ranging from architectural exploration up to post-silicon debug. Jasper focuses on formal verification, it is not just one of many products, so we can really help you change and improve your verification approach. If you are finding that your management thinks there is never any time during, or in between, projects to use a new technology or tool, contact us and we can share some very convincing information on real-world ROI! Please visit http://www.jasper-da.com
I have to say I know and want to use formal verification method. I just don’t have an enough time to learn and set this environment. Most of verificationer spends their most of time in a pre-silicon verification. They are just plain busy in architecting and building testbench using simulation and a bit of emulation. In fact, that is what the upper management wants. In other word, no time allowed on another method to learn. Management has a stick to their habit not to go over their visible experience, unless they are forced to explored. Big problem! I am trying not do go in this path. Any easier or quicker way to get a good grip on this formal method?
I can see the value add for formal verification and would encourage it use. I do see that oftentimes there are resource constraints on the development team and adding another tool is great but requires: people resource, tool investment capital, and time to learn. I could see where many would opt out of the formal verification path only later to come to understand its value.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.