This is a great technology as far as it goes. Very useful for a great many applications. However in a fully switched capacitor system, the sampling rate etc. is limited by the noise created to the point where it can no longer be filtered out. This is somewhere between 800KhZ to 1MHz in PSoC 1 devices.
@Dr DSP, try to think of this as "analog DSP." I know that sounds awkward, but what I mean is it's a sampled data system, just like DSP, except it's not quantized. So the sampling theorem applies, and you have all the usual DSP concerns like avoiding aliasing and correcting for sin(x)/x distortion due to the zero-order hold.
Since the MOS switches are not ideal, they do make a noise contribution, but it turns out that a switched-cap resistor generates the same noise voltage as a physical resistor of the same value.
Is there a maximum frequence limit to operation based on the need for the Caps to be driven by a clocked circuit? It might be in the article somewhere but I counldn't easily find it...
Are there other limitations- power, noise, etc? So much clocking would have a few downsides I would think...
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