The wait is going to be longer for using EUV at 16nm. At Nikon's LithoVision San Jose this year, Nikon made announcements that EUV's availability at 16nm (they missed for 22nm!) is pushed to dates 2012 or later.
I like Mr. Sawicki's take on 3D. Sure enough, the most optimum and reliable 3D stacked system is the one that is homogeneous. But this is years away from productization. There needs to be a sea change of capabilities and features implemented in the current 2D (or 2.5D) EDA tools. Circuit simulators need to work side by side with field simulators (emag, thermal & stress) in a practical way (read: shouldn't take several days to simulate!) to make the design process manageable.
Heterogeneous stacks on the other hand are seeing a good pace of development. There are several MPW's on the way that help researchers and product developers test their designs. The design challenge here using existing EDA tools is by no means a lesser challenge than the homogeneous stacks.
Dr. MP Divakar
16nm? Sounds like very early. First is not always better for business in this case...plus how many companies can really do 16nm silicon processing? 3? 5? so any EDA development is really custom for a particular foundry considering large difference between them, at least initially until some equipment standardization happens...Kris
Need to spread your net wide below 22 nm. Even 3-D is not a for sure thing. Trend extrapolation has its limit, that limit is about now. Double or even multiple patterning is the most natural choice for now, even if pushing Moore's law more slowly than before.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...