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re: Out of billions, one bit in error
simon_at_avalon   8/26/2010 8:22:07 AM
Yes, the Weller 'splat test' is always useful when tracking down or trying to generate occasional errors. We keep one of the old irons for this very purpose. Another interesting source is from the (plastic) wheels on office chairs running on a polished lino floor - if the lights are out you can see the sparks as you move.

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re: Out of billions, one bit in error
zeeglen   8/25/2010 9:28:42 PM
Good catch. How well(er) I remember similar soldering irons with the transformer in the light blue stand. Every time we ran bit error tests on T1 6000 foot lines all soldering irons in the vicinity had to be turned off. One of those irons did turn out to be very useful in a test fixture I built to generate electrical power line transients. This was nothing more than a chattering relay (it's contacts in series with it's coil) to switch the AC line on and off to the soldering iron. Any time this could be shown to cause bit errors in a system under test we knew the shielding and/or power line isolation needed work. It also served to prove to management that bit errors are indeed caused by power line transients getting into the twisted pair and not necessarily through equipment faults, so they did not demand 100% error free tests.

old account Frank Eory
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re: Out of billions, one bit in error
old account Frank Eory   8/25/2010 8:42:12 PM
Great story Glenn. This takes me back to the early days of my career when I was testing satellite modems. Those last couple of data points on the BER vs. Eb/No curve took forever to get. We never had issues with EMI from the soldering irons, but we did run into some interesting environmental influences that were only measurable down at the 10^-11 BER level...

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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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