TSV involves ultra-thin wafer handling and dry etching - both of which exist. Through-put is a challenge.
system integration presents a different set of assembly challenges, as well as reliability issues.
I worked on this 5 years ago and thought it was more than 5 years away, but momentum is building.
Heat would be an issue if a cpu is in the stack. But I've seen heat sink for dram as well, a little to my surprise. Taking things off chip in 3d looks counter to SoC trend. Maybe it's more suitable for memory. But even there 3d gets competition from wide interconnect in top layer.
I don't think the heat dissipation is that a big a deal. Today you have memory, logic/memory and other 3d stacks. They have been shipping for a while. Only difference is they are wire-bonded, not connected using TSV.
There are other significant issues, such as via processing costs and lack of standards that are the bigger inhibitors.
In addition to what greenpattern has mentioned I imagine the need for common design tools and common die interfaces from the different companies will be necessary. But the big players will still be driven to have their own proprietary techniques. It will be interesting to see how all of this comes together sooner or later.
Will 3-D require new fabs? Or can existing fabs support TSVs? This seems to be an interesting technology, no doubt, but of use only to those companies that make huge devices (in terms of silicon real estate) such as Intel. I am sure the majority of the semiconductor companies out there are nowhere near the mark where 3-D will result in significant cost savings for them. I also don't think power savings alone will warrant a shift towards adopting 3-D.
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