The Text States:
"The 130-nm device has demonstrated the ability to have a maximum write voltage of less than 1.6V, a program current of less than 60uA, a program time of less than 5us per cell and an erase time of less than 10us per cell."
Well, ion conduction implies to me serious limitations in speed. I'm guessing that While in graduate school, we used millihertz frequencies to characterize ion conduction! Of course, I don't expect this to be that slow. However, milliseconds programming time is not unlikely.
I can not understand everything that is written in this article as there is a lots of prerequisite knowledge involved but i am easily impressed with the technology with keywords like low power consumption and continued scaling of Moor's law. However, in the end, it is mentioned that earlier efforts by Micron and Infineon did not fly so i wonder what would be different this time that this technology will fly.
Adesto's spec information is hard to find. CBRAM is a very interesting technology. I think it may even be a potential memristor platform. But from what I know of CBRAM, while it may use a Cu backend, the system cannot be all copper, there has to be tungsten or aluminum as well.
Samsung would be the only conceivable foundry to offer 20-30 nm half-pitch, since it is already there as a memory company. TSMC, GF, UMC are too focused on logic which is two generations behind in half-pitch.
The investigation of new memory technologies is important. But a key barrier is GB capacity is tied to 30 nm half-pitch process which is only established in dedicated memory (NAND, DRAM) lines. It would be nice if foundry could support such high densities. Otherwise these Mb-scale demos may still leave skepticism about scalability to higher densities.