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phoenixdave
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re: IBM 'fab club' denies problems with high-k
phoenixdave   9/29/2010 10:10:05 PM
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Gate first seems to make more sense from a foundry perspective, since it can be integrated into an existing process line without too many changes. The foundry business has to focus on integrating the needs of many different clients and products, not just one (like microprocessors). Low-cost integration across a product group is essential for success, otherwise equipment and production costs will eat you alive.

wilber_xbox
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re: IBM 'fab club' denies problems with high-k
wilber_xbox   9/29/2010 7:15:45 PM
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Here again TSMC seems to have a upper hand by following the footsteps of Intel. As Intel has shipped two generations of high-k dielectric based processors so the technology is proven. Only after AMD ships its processors, we will know which technology is better and has a smooth road ahead.

mike655mm
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re: IBM 'fab club' denies problems with high-k
mike655mm   9/28/2010 11:19:30 PM
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Atom, of course, also targets handhelds where very low power is a must. Todate, though, Atom is still made with the 1st generation 45nm high-k process. It'll really start getting interesting when it comes out on the 2nd gen 32nm & 3rd gen 22nm processes

resistion
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re: IBM 'fab club' denies problems with high-k
resistion   9/28/2010 3:24:21 PM
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Intel's high-k process, if I recall, has many extra process steps and complexity, including dummy polysilicon gate removal, and multi-metal deposition. Even so, it became a high-volume process. Yet Atom still consumes too much power for some. It will be interesting to see AMD gate-first vs. Intel gate-last CPU benchmarks.



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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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