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re: FPGAs advance, but verification challenges increase
KarlS   10/23/2010 5:55:48 PM
At the re-usability aspect is stressed, but that is not really a big factor in most designs. In fact, a guru once told me that he had never been able to re-use a hardware design. A needed companion to this verification approach is a design entry/simulation flow based on modular design. If only there were a way to separate the functional design and simulation from the compile, synthesize, place & route, timing analysis, generate RTL morass. Simply realizing that the FPGA consists of data flow and that "cloud" of combinatorial logic leads to data flow is easily understood and not error prone while control logic involves sequences of events and conditional events that are error prone. Boolean Algebra offers an accurate concise way to define control logic and can easily be simulated/interpreted directly to provide functional verification. Connecting partitions/modules together with qualified names as OOP languages do for classes can produce designs that naturally migrate to the GateRocket methodology. I have proposed a syntax for Boolean input and have a prototype simulator available.

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re: FPGAs advance, but verification challenges increase
dorecchio   10/18/2010 12:45:45 PM
We have known for some time that ASIC designs have experienced a gap between the available ASIC gates and the capability of design teams to verify them. The same is now true with advanced FPGAs but now the problem extends into the lab during design bring-up. I am looking forward to learning more about your challenges with FPGA Verification and Debug.

Max The Magnificent
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re: FPGAs advance, but verification challenges increase
Max The Magnificent   10/18/2010 9:20:26 AM
I must admit that ever since I first discovered GateRocket and their RocketDrive and RocketVision technologies I've been rather impressed. The idea that when you discover a problem in the design running in the physical device, you can re-run with most of the design in the physical FPGA and selected blocks in both the simulation world and the FPGA and compare the outputs of those blocks (and internal signals) to quickly spot where the discrepancies are coming from ... I wish I'd thought of that!

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