The work of Ovshinsky and LeComber that I was referring to was the observation of small step like discontinuities in the pre-breakdown threshold switching characteristics.
It was easy at the time to dismiss these as dirty contact effects, but there was always one troubling problem with that explanation. The steps were always equally spaced on the voltage scale, or exact multiples of that spacing.
About ten years later Professor Peter LeComber at U of Dundee, Scotland reported observing similar effects in amorphous silicon. (Published in the Journal of Non-Crystalline Solids).
My understanding is the explanation in both cases was the result of the formation of short nano-filaments in the conduction path.
Of the earliest observations, other than a dirty contact effect, the possibility that the conducting region was moving across regularly spaced atomic surface layers or crystal boundaries was also offered.
I guess the point I was trying to make is that electrical or electronic manipulation of structure, albeit on a nano scale, by the selectively formation and removal of detectable nano-filaments might offer a more stable NV memory than an amorphous to crystalline transition. That is the structural shape on the nano-scale is the memory.
The behavior was not impossible, it was observed, in one case by this writer, it is only the explanation may be wrong (impossible)
The L3 cache miss rate can be low enough that DRAMs are hardly accessed and mostly refreshed. This is an ideal target, the less the main memory is accessed, the higher the system performance. In that case the DRAM refresh cycle rate would testify the minimum endurance.
rbtbob: Wow, "some of Stan Ovshinsky's early work on devices that exhibited seemingly impossible behavior?" Really?
Are you sure? Because it has been very well documented that Mr. Ovshinsky had (and still has) the habit of fabricating things, facts, and numbers.
By the way, why not include some dilithium in the mix, as well? A cell design that involves dilthium crystals is sure going to be extremely efficient and very well regulated.
Mr. Neale, I believe you are performing an important service it playing the devil's advocate against the often rosy claims of amazing developments in PCM, but you shouldn't lean so far to the devil's side that you cease being an honest broker. I was intrigued when in a recent post you suggested the researchers should revisit some of Stan Ovshinsky's early work on devices that exhibited seemingly impossible behavior.
I assume that the broad-scope use of "materials which may be switched..." in item 0038 is actually a disclosure of the fact that they are working with other mixes of elements that may change resistance without actually making a crystalline to amorphous change. The materials science papers are full of descriptions of "stuff" that does some kind of funky change in the crystal structure that causes a significant change in resistance. (from either current, heat or laser pulse) The cell design in the patent app seems simple enough, all it needs is the right "stuff" as the memory material. My bet is on a mixture that includes terbium.
Too many cooks spoils the food, may be Too Many Different RAMs/ROMs with different Technologies and Different Materials will not spoil/corrupt the Data or the Life of the Data.
So ReRAM and PCM new names are coming up but it will still require a long path to get accepted for production.
The justification statement #016 that I cited was an admission of problems related to PCMs based on chalcogenides and from the very heart of the PCM action.
While PCM is a resistive memory, the term is nowadays more used colloquially to describe NV memory types based on other mechanisms. I thought I had acknowledged the resistive memory statement when I suggested those applying for the patent were hedging their bets in that same “Hoist by their own Petard Paragraph”.
I am not a patent lawyer (attorney) but for me the use of the term resistive cell memory in statement #017 is the all embracing way of providing protection for the new structure in its use as both an improved PCM and for any of the competing NV resistance memory devices (ReRAMs) and (PMCs). Only time and money will tell if it solves the PCM problems it acknowledges.
There are three champion groups, one at Samsung, one at IBM, and Numonyx. However, my understanding is the materials they use are all prepared differently, not to mention their structures. So currently, none of them can second-source each other, just due to significant process differences.
Replacing DRAM is a stronger claim to make than replacing Flash. How many cycles does phase change memory have to show to qualify as a DRAM replacement in servers? The current Numonyx spec of one million seems a tad short.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.