Hi Frank, I think you are dead on, and in some ways the point I was trying to make: that it is designers who can impact power more than anything else, including implementation technologies. But if you have a good designers who knows what to do to create the best power friendly architecture, then everything else just adds to his ability to create a low power solution and then - yes an ASIC will have lower power than the same implementation in an FPGA solution.
Good article Brian, and I think you said it best: "Power optimization starts at the system level and we then try and fine tune it as we go down the levels of abstraction."
System-level optimizations have always had the biggest impact on the end result, whether the cost function being minimized is area, prop delay, power, or all of them simultaneously.
That doesn't mean we don't need low-leakage transistors, clock gating, dynamic voltage & frequency scaling, etc. We need every tool in the toolbox to win the war against power.
The "optimize for low power" settings in synthesis are good at what they do, but are never going to re-write your RTL to implement a lower power architecture, and are likewise not going to throw out your general-purpose processor and replace it with a state machine.
For those types of optimizations -- thankfully -- we still need smart human beings!
To the point of your article: yes, an ASIC will always have some power advantages over an FPGA with the huge caveat of "all other things being equal." But all other things are almost never equal, and it is quite feasible that one team's FPGA solution to a problem will be a lower power solution than another team's ASIC solution to the same problem.
I love the word Oxymoron -- it just struck me that i didn't know it's origin, so I bounced over to www.Dictionary.com to discover that this little beauty comes to us via New Latin from the Greek oxus, meaning "sharp" and moros, meaning "stupid".
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