We all have more than 10 years of experience in chip design and believe me know exactly what does the chip design mean (including custom design, semi-custom and full-synthesis methodologies). Our current flow is really not just about the functional design and does have all of the design phases you mentioned above. We even run the fast spice simulation of the full chip - something that is not that common in the industry (as you probably know).
One thing which is probably different in our company is that we really don't try to fight the tools and consider all of the design aspects (synthesis, floorplanning, pnr, etc) as early as at the architecture definition phase of the project.
I'll be glad to discuss with you more about our methodologies if you wish - just send us an e-mail "first_name"@adapteva.com
Is any design not hierarchical ? But once it's synthesized, it's flat. A chip is essentially
flat even with floorplanning. ATPG, memory bist,
logic bist, boundry IO cell/chain insertion are
all flat. And my favorite part, Test Pattern Generation is flat. A big part of chip design is
completely orthogonal to the fucntional design.
Of course, I've heard of magical scripts that do
all of it with one click.
Thanks for posting a question on one of my favorite topics, design methodologies:-) The secret to the speed of our design flow (and there really is not secret) is having an extremely hierarchical design flow. We built our architecture and design methodology from day one to be modular and scalable (ie hierarchical). It doesn't work for every design type but it's worked extremely well for our regular architecture. Here are some benchmarks for the Magma tools:
-block level synthesis and analysis, 6-9 hrs. The key is to partition the design into small blocks (100k-200k gates at most). Then you farm out these small jobs in parallel.
-top level DRC, 30 minutes
-top level chip assembly of all the small blocks, 1 hr
Not to minimize the achievement, I have a question.
I was involved in a similar sized SOC design using Magma tools also. We had benefit of many parallel computers and full SW from Magma. Simply running the design cycle (STA,clock tree insertion, setup/hold fixes, foirmal checks, DRC/LVS, etc) took much longer than 24 hrs of CPU time - even if there were no errors to fix. How could this development be done so quickly with lesser suite of tools and computers (I am guessing that). I guess I am skeptical that these large SOC designs can be done so quickly and error-free .. but maybe we are dealiung with true gurus here .. Just curious.
Thats the spirit, which will guide and lift to the destination, more over hats of for the self confidence.
Really inspiring one for all front end and back end designers, may Andreas stood as role model for all techi guys.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.