This story just blows me away! I cannot tell you how impressed I am. Until I heard this I would have said that the days of an individual (or a small group) inventing and creating a new chip on their own were long gone -- but this tells me that the days of the garage inventor are still with us and I find that to be incredibly uplifting!
I have had the privilege of working with Andreas before he set off on this crazy venture. Only he could pull off something like this. Apart from his brilliant technical skills he has a wonderful personality.
Andreas, I’m very happy for you and I wish you the very best going forward!
True hands-on, Deep Engineering; coupled with perserverance, self-belief, and intelligent direction of the effort to an end product need! The parallels and contrasts with Chuck Moore's work over at GreenArrays.com are fascinating, although Chuck wrote his own silicon compiler/GDSII layout tools because that was the only way to understand how fast silicon could actually go, and how to reliably achieve that potential performance in production. Juries are still out on commercial success for both efforts although of course we wish them well!
So Max, where are these guys working out of? Their website lists an address of Lexington, Mass., is that where Andreas lives? Just curious because Andreas, Oleg, & Roman are not very common in the US, and the whole time I was assuming you were talking about a European company.
Hi there -- I just glanced over my posting and I don't see anything that would indicate/imply a European company. Yes, Andreas lives in Lexington, Mass (I assume Oleg and Roman do too -- but I never thought to ask). When you say "Andreas, Oleg, & Roman are not very common..." I assume you mean "*The names* Andreas, Oleg, & Roman are not very common..." as opposed to the people (grin). Well, my real name is Clive and that's not very common in America either (which may explain why I so often end up at conferences sporting a badge that says "Olive" -- as you can imagine I get some funny looks (I can only hope they are caused by the badge [grin])
Thanks for all the positive comments! It's been a long journey but things are really coming together now. You'll be seeing some pretty cool announcements from us soon..
For my fellow chip designers with dreams of building the next great widget, my advice is to not believe the hype. There are a lot of skeptics out there. Just go build it!
The guy has got the magic touch. All hail the god of design! But frankly, the rest of us idiots
don't do this because our designs often have bugs
of logic or layout so we can't get our designs
through the tools so easily and we have trouble
funding our efforts.
But best wishes to Adapteva.
Thats the spirit, which will guide and lift to the destination, more over hats of for the self confidence.
Really inspiring one for all front end and back end designers, may Andreas stood as role model for all techi guys.
Not to minimize the achievement, I have a question.
I was involved in a similar sized SOC design using Magma tools also. We had benefit of many parallel computers and full SW from Magma. Simply running the design cycle (STA,clock tree insertion, setup/hold fixes, foirmal checks, DRC/LVS, etc) took much longer than 24 hrs of CPU time - even if there were no errors to fix. How could this development be done so quickly with lesser suite of tools and computers (I am guessing that). I guess I am skeptical that these large SOC designs can be done so quickly and error-free .. but maybe we are dealiung with true gurus here .. Just curious.
Thanks for posting a question on one of my favorite topics, design methodologies:-) The secret to the speed of our design flow (and there really is not secret) is having an extremely hierarchical design flow. We built our architecture and design methodology from day one to be modular and scalable (ie hierarchical). It doesn't work for every design type but it's worked extremely well for our regular architecture. Here are some benchmarks for the Magma tools:
-block level synthesis and analysis, 6-9 hrs. The key is to partition the design into small blocks (100k-200k gates at most). Then you farm out these small jobs in parallel.
-top level DRC, 30 minutes
-top level chip assembly of all the small blocks, 1 hr
Is any design not hierarchical ? But once it's synthesized, it's flat. A chip is essentially
flat even with floorplanning. ATPG, memory bist,
logic bist, boundry IO cell/chain insertion are
all flat. And my favorite part, Test Pattern Generation is flat. A big part of chip design is
completely orthogonal to the fucntional design.
Of course, I've heard of magical scripts that do
all of it with one click.
We all have more than 10 years of experience in chip design and believe me know exactly what does the chip design mean (including custom design, semi-custom and full-synthesis methodologies). Our current flow is really not just about the functional design and does have all of the design phases you mentioned above. We even run the fast spice simulation of the full chip - something that is not that common in the industry (as you probably know).
One thing which is probably different in our company is that we really don't try to fight the tools and consider all of the design aspects (synthesis, floorplanning, pnr, etc) as early as at the architecture definition phase of the project.
I'll be glad to discuss with you more about our methodologies if you wish - just send us an e-mail "first_name"@adapteva.com
The last time I remember something like this was working with a team of 10 genius for 1 year to come up with 1/4 complexity of this project. There also we started from 0..and everything was free..as it was an academic institution....
Salute guys.. you rekindled a hope that garage entrepreneur in vlsi too can be there...a hope that was squashed long time ago.
Can't really express how happy and grateful I am to read this story!!! This is the type of complex protoype in 2004 I tried to do myself but with no success due to lack of funds and patience. I applaud your persistence and your mission. With this experience, you will get back your the funds you used in the long run, because this experience is worth way more than the money you invested. Venture capitalists are usually not the way to go for the true breakthroughs... too much politics strangles innovation.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.