Resistion-I think, at say the 32nm process node they would cut a 20nm sub-lithographic pore in the dielectric then deposit a 3nm film of GST. Back fill the central core using a dielectric film deposition over the GST then chemically mill flat and deposit the upper electrode. Easier said (writ)than done, especially the circular sub-lith work, I agree.
Please do not take my artist's impression too literally, it is more to justify the use of link results in the analysis technique and the new name WAL-PCM.
The diagram graphics are impressive as always. I think one issue with this WAL structure is the fabrication. It looks like some ring-shaped mask is used to etch the structure. The etch damage to PCM especially so thin is a well-published phenomenon. The design might be good, but the execution may not go through as desired.
Editor's Note: We recently published what apparently was an extremely interesting statement with respect to a patent application and problems associated with phase change memory (PCM). The article and comments added further to the scalability questions already under discussion on the Memory Designline and EETimes. To explore this issue further, we asked Ron Neale to provide his view on if there might be any merit in the new patent and its associated structure. This is his response.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.