R G.Neale: Apparently, Samsung carefully reads your stuff. They have now removed that unfortunate 512Gb marketing brochure, even though I did not contact them. Somebody there must be in a panic mode. With Flash prices dropping again and Spansion out with their 2Gb NOR at 65nm, Samsung must know their window of opportunity is rapidly shrinking.
Volatile Memory-I think that is most likely a translation or typographical error on the part of Samsung or their brochure editors. Most of us are aware where Samsung are in terms of PCM bit density in products. They are almost certain to be referring to their 512Mb PCM. I am sure they will correct it if and when they are made aware of it.
I think the next important PCM benchmark for Samsung is ISSCC2011 in February next year. With the burning question, will their paper be followed by a 1G-bit PCM product announcement? Or will it just record a notable PCM technological Tour de Force at 58nm. In a similar vein to the Multilevel Cell PCM that was presented by STM at ISSCC2008. Whatever it is, for me it will be nice to know for the 1 G-bit the PCM contact diameter and reset current density and write/erase lifetime for my records.
Somobody just brought to my attention an interesting document prepared by Samsung on October 4th, 2010:
Page 3 states: "Samsung’s 512Gb PRAM is combined with Mobile DRAM to deliver performance three times faster than NOR-based MCPs, making it ideal to quickly process large-size multimedia
The "three times faster" is obviously a lie, but hard to prove given that the only PRAM chip in a cell phone has been destroyed.
However, it is obvious that Samsung lied about PRAM being 512Gb. It is just 512Mb. Samsung exaggerated by a factor of 1024x.
And, apparently, nobody has noticed so far. People must be busy installing those chips into fake phones instead of reading marketing materials.
Great job, Samsung!
When Intel made the statement a few years ago that PCM was scalable to 5 nm (which I think is more aggressive than Samsung's 15 nm), they were referring only to using a probe tip to excite the phase change, as the demonstration. I think it doesn't mean directly translating to a 5 nm connected random access device. Likewise, probably most PCM studies are established with 15 nm and thicker films. I don't think phase change happening as low as 5 nm can be justified to say PRAM can scale to 15 nm and beyond. There are other considerations not related to the memory as well. Such as will the signal travel to an adjacent line before the memory cell?
Truth or lies, if the E2550 phone with the PCM (see EETimes) did actually originate from Samsung then there was some truth in the statement of Samsung's Kinam Kim at IEDM2010. I recently added a comment my own comment to the EETimes piece on the finding of the PCM in the E2550 phone. It would appear that my prediction on the way the appearance of the PCM phone might be used by Samsung, at ISSCC2011, was fulfilled almost to the word at IEDM.
To me, more important than scoring points, when senior Samsung representatives make comments like “ PCM will scale to the 15nm node and beyond” it would be useful if they would indicate the current density they think will be involved and the structure. If Kinam Kim is using ITRS forecasts, I think they are based on the PCM dome heater electrode structure-the very structure with the heater that the WAL-PCM patent discussed above in PCM myth Part 3 teaches us it is too difficult to fabricate. Current density numbers for PCM pore at sub 30nm lithographic extracted from recent IBM paper on PCM at VLSI2010, down to 20 nm indicate over the contact diameter (CD) 70 to 20nm the current density would appear to be 2.8x10E7A/sq-cm (+/-0.1). I would be tempted to suggest, in accordance with the prediction of the PCM Myth Part 1, that this is flat and a minima. Best case downward extrapolation of that data to 15nm node with pore contact diameter (CD) of say 12nm is not likely to provide much of a reduction in current density. So perhaps they (Samsung) are planning to use the link structure “beyond” those dimensions! Whatever the structure, a need to know in fine detail what happens to molten GST at the current densities of a cathode arc spot (see E Hantzche 2006) is urgent as is the unified model of PCM operation.
That is a quote from the paper. He had different emphasis in the presentation. It was no longer on PCM or STT, but on 3D NAND (and 3D versions of other technologies, incl. ReRAM). However, ReRAM is very early stage, compared to PCM. You should be aware, Samsung works on a lot of different, almost self-competing technologies at the same time.
Apparently, Samsung lied during the International Electron Device Meeting (IEDM) keynote again:
"PRAM is now being adopted in mobile phone applications as a code storage memory. The advantage of PRAM is that it can be scaled down to the 15 nm node and beyond."
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.