The concept isn't new - there are already reset/watchdog ic chips often used in such designs. They allow communication with the Application processor to set-up a timer, whilst also providing protection for the SoC by holding the reset until the power is stable. It's know for years so above sounds more like a reminder than 'innovation'..
The last handheld device I worked on had an FPGA. Software was expected to detect the "power" button after 3 seconds to provide the usual graceful shutdown, but for safety we put in logic to shut off power if the user holds down the button for more than 5 seconds. It's hard to imagine phone designers leaving out such a failsafe feature. Especially since Microsoft has conditioned users to expect a "reset button".
I always scroll to the last page to check the writer's byline: ahah, its a Fairchild guy selling chips. Fair enough, but some of his fixit examples are just fixing terribly bad design in the original smartphones, ie the white screen of death; having to remove the battery... seems they never learn.
I hereby declare that my preference is for a separate watchdog device, but I'd use an on-chip device provided it was independent of everything except the power rails. (I am assuming we are not talking about hi-rel devices here by the way.)
A Book For All Reasons Bernard Cole1 Comment Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...