Dear Mark, I work for Dr. Domic in the Synopsys Implementation Group, and we have spoken about your article. Since he’s traveling abroad, he requested that I submit this clarification on his behalf:
"In my presentation, I just wanted to raise a flag : the enthusiasm for TSV and 3D IC integration may have hidden some drawbacks that, in my opinion, should be carefully weighed. Cost is one of them.
Drilling the TSV has a 5% additional cost per wafer; for the sake of comparison, SOI has a 5% additional cost per wafer, and high-k metal gate has a 10-20% additional cost per wafer.
Of course, manufacturing costs do change dramatically throughout the lifespan of a process. This is just a snapshot of the situation today, and yes, other factors besides these costs must be accounted for.
My talk focused on the design and EDA aspects and the implications of TSV and 3D IC integration on key tools in the design flow (for example place & route technology), suggesting that a more evolutionary, phased approach would be more feasible in all respects."
Dan's number on per-via costs is perhaps an admirable first guess, based (as it must be) on estimations of hypotheticals (since none of this is in HVM yet, we're guessing the real area penalty for KOZs, yield losses, EDA overhead, etc. as previously mentioned by Warren); Phil, if you disagree with Dan's number then let us know your assumptions and your number. Regarding the, "it buys you 1-2 nodes" argument, that's nice...but, "it's a one-time buy you pay for with each chip in perpetuity" (says a VP from a large IDM).
3D has been "happening" for years with wire-bond stacks and PoP, and now TSV in passive Si-interposers are reportedly in pilot ramps. Regarding the eventual use of TSV in active Si dice (I presume this is what Phil means with the term "3DIC"; I like to use the IMEC terminologies of "3DSIC" for global-level, and "3DIC" for local-level vias in active Si, but in either case), all publicly known high-volume commercial demand is being met using wire-bonds or Si-interposers or PoP or TMV (all lower-cost and lower-risk "2.5D" technologies), so 3DIC may be "happening" in R&D lines and niche fabs (as has been happening for years), but it it nowhere near commercial HVM (sorry Tezzaron, but 100 wafers/month is merely "pilot" or "niche" work). You can find more on this and other manufacturing technology developments at BetaSights.Net in recent posts.
PS, in keeping up rigor in terminology, a power amp with a TSV cannot count as a "3DIC" since it is a discrete chip not an IC. Also, the blind-vias through a MEMS or CIS cap (relatively trivial 20-year-old WLP way to open holes for wire-bonds) are nothing like TSV in 3DIC (zero functionality similarity). Let us eschew obfusication. Cheers.
Mark - you are cherry picking selected comments. 3D like any other technology depends totally on how you do it. The 20 cents per pin number from Hutchenson is absurd. The key recent message on 3D is that prices will be in line with what is needed because this is being driven by Qualcomm, Nokia, TSMC, Samsung, Elpida etc. and they are getting costs in line. What is buys you performance wise is 1-2 nodes ech of which would cost you $6-10B. As long as there is not an as yet undiscovered electrical performance show stopper, 3DIC is happening ! For all the latest on 3DIC link to "Insights From the Leading Edge"
The technology could be definitely used to make all the normal semiconductors chips only if there is an advantage of technical performance or the reduction in the cost. But at this moment TSV has lot of impact on the cost and so it is wise to use in MEMS, Image sensors since it has some technical advantages.
It looks as though a mix of approaches are used in calculating costs within the article so not particularly comparable. The lead-in cost impact statement is purely accounting for the additional wafer production costs and doesn't even look to account for the opportunity cost of silicon area consumed by TSV's that could have been used for other functions. Although not specified, none of the cost statements look to me to be trying to account for NRE (as I'd hope they wouldn't). But the real extent of the cost adder must certainly at least address wafer production and associated opportunity costs, assembly and assembly yields, and test.
Once the EDA tools for TSV designs is available rest of the things will fall in place due to economic considerations . Also , in this industry lot of decision takers wait for methodology to mature before jumping in .
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