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re: 3-D chips moving out of 'PowerPoint' era
Patk0317   12/12/2010 12:10:55 PM
I attended Ivo Bolsens keynote at FPT in Beijing where he described the Xilinx TSV technology. Sounds very promising and very real. This will allow massive SOCs to be realized in programmable logic.

Don Scansen
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re: 3-D chips moving out of 'PowerPoint' era
Don Scansen   12/10/2010 4:23:42 PM
This "PowerPoint" analysis is great. I think it's better than my Dew Point analogy that I have been working with at my blog. Dylan's point is so true. I think I have been through that Monday morning slide deck myself. So many things seem to begin and end in the Microsoft software. Whether it's collecting thoughts, planning a strategy or actually communicating the message in the end, it's often "Death by PowerPoint." Engineers and others who tire of this, but may need to use the software and the medium for real purposes should check out an excellent presentation by that title on SlideShare. Just Google that title. Hey, it isn't going to get anyone over the vaporware hump, but better presentations might reduce the market for anti-depressants. And that makes me wonder if anyone has compared the related effectiveness or cost-benefit comparison of water-boarding versus PowerPoint.

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re: 3-D chips moving out of 'PowerPoint' era
kdboyce   12/10/2010 6:35:24 AM
A similar joke is to tell a customer we will put our best Powerpoint engineer on the job. That aside, regardless of the interconnect between the layers, each layer will generate some heat. The TSV's and the programmable anti-fuses of NuPGA (http://nupga.com/images/NuPGA_3D-FPGA_100129.pdf) will have to conduct the heat to the base wafer, and also the top wafer (assuming a heatsink contact there). Otherwise, one is restricted to very low power devices. While there is clearly products that can benefit from the approach, the holy grail would be to put any function block anywhere necessary in a 3-D structure, truly building a system in a block. Nothing says the individual wafers have to be the same process so long as the inter-connects do their signal and heat transfer functions. Oh...and those darn I/O leads. Yeah...we gotta get them to the outside world too.

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re: 3-D chips moving out of 'PowerPoint' era
mcgrathdylan   12/10/2010 6:11:24 AM
Frank, I like that one. Good joke. I would also point out that we all know some people who are so accustomed to using Powerpoint as a crutch and talking through slides that I bet if you asked them about their weekend they'd just as soon answer by walking you through a deck.

old account Frank Eory
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re: 3-D chips moving out of 'PowerPoint' era
old account Frank Eory   12/10/2010 6:02:52 AM
It's great to see that 3D TSV is making progress, despite the fact that "Powerpoint engineering" is rampant in many realms of our industry -- not only 3D TSVs. Just ask any marketer what the customer wants for his next SoC, and you can have beautiful Powerpoint slides within a week, showing the finished product as he or she envisions it, as if it were already in mass production. Back when I used to spend some effort on system to silicon design methodologies, we used to joke about the next phase being Powerpoint-to-silicon design methodologies. It's still a joke, but still there are some people who don't get that.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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