Maybe this example might help clear up some of the "huh?!" discussion: Your task is to HLS a block that crunches data in a certain way, and is interfaced into a certain system environment.
For the crunching part, you want to use the HLS tool to help you examine lots of microarchitectures, meaning implementation possibilities (various data widths, depths of pipelining, etc.). You may even want to create two or three different implementations at different price/performance points, but the tool must create the RTL for all of those different implementations. You only change a few microarchitectural parameters, pipeline-depth, for example, push a button and out pops radically different RTL.
In the meantime, however, there are interfaces to the world around that algorithmic portion that absolutely must proceed according to a very exact, and possibly intricate, timing definition. You have to ensure that those timing concerns are never violated. It's possible, for example, that a certain implementation of that algorithmic logic will not be able to process the data quickly enough to satisfy the data rates of the interface.
If that's the case, we want the HLS tool, not the designer, to limit the available choices of microarchitectures so that the bandwidth requirements of the interface will never be violated.
This article shows that SystemC is required to do any real design. Since SystemC is a class lib of C++, thus a superset, and since SystemC processes can contain pure untimed C++ code, shouldn’t the article be titled: “SystemC is the language of ESL”.
Also why does the article avoid the very popular TLM standard which enables easy separation of the interface from the computation and yields large simulation speedups (instead of inserting an RTL interface from a library)?
For those interested in how to do production design with SystemC, there's an archived EETimes webinar by Mark Warren aptly titled "Practical application of high-level synthesis in SoC designs".
"... but it has been proven that it is easy to extract parallelism from sequential sources."
This will come as news to everyone in the High Performance Computing community, who have been attempting to do this unsuccessfully for over 40 years. It will also be news to the authors of the numerous textbooks on parallel algorithms (if extracting parallelism was easy, why would we need them?)
Sam Fuller (CTO Analog Devices) and co-author Lynette Millett have the opposite opinion: "Experience has shown that parallelizing sequential code or highly sequential algorithms effectively is exceedingly difficult in general." in their article "Computing Performance: Game Over or Next Level", IEEE Computer, January 2011, pp. 31-38, reporting on the NSF-sponsored study by the Computer Science and Telecommunications Board of the US National Academy of Sciences.
Why is the example given for these HLS tools always a trivial datapath block such as an FIR filter?
It gives the impression, rightly or wrongly, that the tools are only good for simple pipelines. I am not losing sleep over those sorts of designs.
DKC - yes, i was a bit perplexed by the title as well. Multiple HLS technologies should co-exist in a single work-flow, not only these. It is really in what application you are designing for and what VnV activities are required- which can really impact the quality of the product and TTM.
What war? SystemC is just a C++ class library. It would pretty lame not to be able to have them coexist.
How about analog and power? When will we see -
"The wait is over: C++ and Spice coexist in a single flow"?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.