Where do they draw the line between fab tools and packaging/assembly tools? I ask because I am currently working on a far BEOL tool that we call a packaging tool. We classify TSV as packaging and pretty much anything after the interconnects. At Intel, everything after the last interconnect layer was 'considered' packaging for 45nm stuff as it was done outside of the FEOL/BEOL 'wafer' fab but still before wafers are diced up. The tools used for some of the first stages of this packaging are not very different from fab tools whereas when you move more towards assembly, they are.
@hkdigital1- you make a good point, which caused me to take a closer look. I determined that I made an error (which I corrected). In September, Gartner said the tool market would be up 122 percent next year (113 percent was from their June forecast). For comparisons sake, Gartner is now saying the 2011 capital equipment market will be worth $38 billion, as opposed to $38.7 billion in the September forecast.
So, Gartner raised 2010 growth from 113% to 131% and lowered 2011 growth from 4.9% to negative 1%. That means their new forecast for 2011 is 17% higher than it was in their September forecast.
Flat tool orders for 2011 coming off record 2010 doesn't look bad.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.