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old account Frank Eory
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re: Intelligently integrated physical design and verification eliminate late-stage surprises and manual fixes
old account Frank Eory   1/5/2011 9:14:01 PM
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Excellent article, and nice to see that Synopsys has implemented this fix-as-you-go methodology for IC Compiler. Engineers sometimes think the P&R tool should simply not create DRC violations in the first place, but as the author pointed out, early versions of the router tech file don't always have all the rules -- so some violations are inevitable when doing a first design in a new process node. This looks like an excellent approach to solving that problem.



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