This is very old news. Memory on logic as the driver for 3DIC has been proposed for years. At Semicon Taiwan this past Sept there were several talks on this including Nokia who stated that JEDEC wide I/O standardization for 3DIC will be ready in late 2011. Contrary to the comments of Mokhoff and others, both Elpida and Samsung had now announced stacked memory products for 2011/2012. 3D is fully underway. To keep up with this on a weekly basis link to: http://www.electroiq.com/index/packaging/packaging-blogs/ap-blog-display/blogs/ap-blog.html
Although the article does not say it explicitly, I assume the wide I/O DRAM is to be stacked on the logic die (SoC) of the mobile device. If we are considering a single layer of wide I/O memory being placed on top of a complex SoC, then we do not need TSV. There are cheaper technologies than TSV, for example, bump based 3D stacking. Alternatively, one can have a feed-through interposer (FTI), between the logic and memory dice, as discussed in the SMAFTI technology developed at NEC.
Last paragraph reiterates it all, about the issues of tools, complexity, integration and standards. It will take a monumental industry-wide effort to come up with feasible production line three-dimensional chips. And it needs design, process and production disciplines to come together to resolve various different approaches. The SIA/SRC collaboration and the SEMI efforts are only a starting point.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.