I would say Intel have shown the manufacturability of gate last!
In terms of pure transistor performance, gate last is the winner for PMOS because it gets extra strain into the channel,
and that is likely the case for NMOS at the 2x node too.
When it is Intel, TSMC v.s. AMD, Globalfoundries, and Samsung, it is interesting just for "bragging rights" only. For companies like AMD, Altera, Xilinks, Altera, nVidia, and Qualcomm, they should care becase they rely on the leading edge technologies from the foundries. When IBM claims the performance advantage of "gate-first", manufacturability and cost are probably more important concerns. Who knows Intel and TSMC will not switch to gate-first in the future nodes?
thank you Mark, perhaps I didn't myself clear...of course we need process scaling for next-gen electronics...what I said is that not too many people care whether you put gate first or at the end of CMOS processing (this was a theme of the article), do you? Kris
I disagree with you Kris. It is critical that chip makers can scale the gate, so we (you and I) can buy next-generation phones, PCs and tablets. It is interesting to know just how chip makers can scale the gate dielectric. I will bet Apple cares. So does Qualcomm. Want more examples?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.