Thank you for the insightful comment. Your analysis is correct. Even though Stellamar’s ADC is digital, like in any design requiring the use of traditional ADCs with the same resolution, special attention must be paid to the board layout to minimize noise and to the power supply accuracy and stability. In particular, the ADC I/O cells need to have a separate power supply. Also, they need to be placed in different banks or, if in the same bank, far away with respect to those used for other purposes to minimize interference. With a careful board design, Stellamar’s ADCs have very good DC performance. Also, compared to other traditional ADCs, Stellamar’s Digital ADCs have the further advantage of offering extremely low offset drifts. If you have further questions, we'd love to hear them. Please feel free to contact us at any time.
AC performance looks good but can you tell us a little more about DC accuracy performance? (Achieving low gain error / TUE for example). This is where I've seen issues with techniques like this in the past. Many of the applicatons listed above required good DC accuracy. The DAC output (FPGA IO supply voltage) defines the ADC input range (reference) but this can vary significantly due to many factors. Also noise from other switching IOs in the same bank can be an issue.
Thanks for the comment. Yes DACs have been mostly digital for a long time and digital DACs are widely used, as opposed to partially digital ADCs, which are not widely adopted since very few exist with usable performance.
You can read a similar work in EDN:
D/A converter ASIC uses stochastic logic
EDN October,1996. pp 86-90.
J. M. Quero, C. Janer, J. G. Ortega y L. G. Franquelo
If you are interested in analog processing of digital signal, I also recommend:
Fully Parallel Stochastic Computation Architecture
IEEE Trans. on Signal Processing. August, 1996. pp 2110-2117.
C.L.Janer, J.M. Quero, J. G. Ortega y L.G. Franquelo
If you are interested in this topic, you may send an email to email@example.com
dougwithau- Based on your example, the settling time will in fact affect the resolution and bandwidth. With the Stellamar IP settling time of the filter is not an issue due to proprietary signal processing.
I have lived with a similar design. The bug ugly thing that was not mentioned is settling time.
This looks like the ADC with a PWM driving one side of a comparator and the analog input on the other pin. The settling time of the RC network that filters the PWM limits what you can measure. If the input can have step changes, then the PWM has to change, wait for the RC to settle and then see if the comparator flipped. Repeat. If the RC settling time is slow, this takes seconds to get any real accuracy.
One thing that helps, and I think Max suggested this in his book, swap the bits from the counter into the digital comparator for the PWM. The PWM output through the RC network is still 50% at 50% duty cycle, but it changes at the count frequency, not 1/2 the total PWM frequency.
I hope that makes sense to someone else.
I could be wrong, the blocks diagrams showed by Stellamar are so generic but the technique appears to be the same used in Xilinx "XPS Delta-Sigma Analog to Digital Converter (ADC)". Our solution use a different approach.
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