Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 5 / 6   >   >>
mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/24/2011 8:30:56 PM
NO RATINGS
acollins, Thank you for the insightful comment. Your analysis is correct. Even though Stellamarís ADC is digital, like in any design requiring the use of traditional ADCs with the same resolution, special attention must be paid to the board layout to minimize noise and to the power supply accuracy and stability. In particular, the ADC I/O cells need to have a separate power supply. Also, they need to be placed in different banks or, if in the same bank, far away with respect to those used for other purposes to minimize interference. With a careful board design, Stellamarís ADCs have very good DC performance. Also, compared to other traditional ADCs, Stellamarís Digital ADCs have the further advantage of offering extremely low offset drifts. If you have further questions, we'd love to hear them. Please feel free to contact us at any time.

acollins
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
acollins   1/24/2011 11:32:59 AM
NO RATINGS
AC performance looks good but can you tell us a little more about DC accuracy performance? (Achieving low gain error / TUE for example). This is where I've seen issues with techniques like this in the past. Many of the applicatons listed above required good DC accuracy. The DAC output (FPGA IO supply voltage) defines the ADC input range (reference) but this can vary significantly due to many factors. Also noise from other switching IOs in the same bank can be an issue.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/21/2011 9:40:14 PM
NO RATINGS
Jose, Thanks for the comment. Yes DACs have been mostly digital for a long time and digital DACs are widely used, as opposed to partially digital ADCs, which are not widely adopted since very few exist with usable performance. Great papers! Stellamar

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/21/2011 9:34:06 PM
NO RATINGS
WSFPGA- Stellamar achieves better performance at a much slower clock. The Stellamar approach is not at all like the Xilinx approach. Stellamar

jose.quero
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
jose.quero   1/21/2011 6:58:59 PM
NO RATINGS
You can read a similar work in EDN: D/A converter ASIC uses stochastic logic EDN October,1996. pp 86-90. J. M. Quero, C. Janer, J. G. Ortega y L. G. Franquelo If you are interested in analog processing of digital signal, I also recommend: Fully Parallel Stochastic Computation Architecture IEEE Trans. on Signal Processing. August, 1996. pp 2110-2117. C.L.Janer, J.M. Quero, J. G. Ortega y L.G. Franquelo If you are interested in this topic, you may send an email to quero@us.es

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/21/2011 12:25:33 AM
NO RATINGS
dougwithau- Based on your example, the settling time will in fact affect the resolution and bandwidth. With the Stellamar IP settling time of the filter is not an issue due to proprietary signal processing.

dougwithau
User Rank
Manager
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
dougwithau   1/20/2011 11:07:44 PM
NO RATINGS
I have lived with a similar design. The bug ugly thing that was not mentioned is settling time. This looks like the ADC with a PWM driving one side of a comparator and the analog input on the other pin. The settling time of the RC network that filters the PWM limits what you can measure. If the input can have step changes, then the PWM has to change, wait for the RC to settle and then see if the comparator flipped. Repeat. If the RC settling time is slow, this takes seconds to get any real accuracy. One thing that helps, and I think Max suggested this in his book, swap the bits from the counter into the digital comparator for the PWM. The PWM output through the RC network is still 50% at 50% duty cycle, but it changes at the count frequency, not 1/2 the total PWM frequency. I hope that makes sense to someone else.

old account Frank Eory
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
old account Frank Eory   1/20/2011 8:26:34 PM
NO RATINGS
Best of luck guys!

WSFPGA
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
WSFPGA   1/20/2011 8:25:33 PM
NO RATINGS
I could be wrong, the blocks diagrams showed by Stellamar are so generic but the technique appears to be the same used in Xilinx "XPS Delta-Sigma Analog to Digital Converter (ADC)". Our solution use a different approach. Walter

studleylee
User Rank
Manager
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
studleylee   1/20/2011 6:35:36 PM
NO RATINGS
Brilliant application!

<<   <   Page 5 / 6   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

10 Top Video Parodies on User Interfaces
Max Maxfield
13 comments
As you may know, the people of Scotland are holding a referendum today to decide whether they wish to remain part of the United Kingdom (UK) or to become fully independent and "go it ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)