Thanks for pointing out this detail. If this has random access as in DRAM, then it could be wired like a NOR. Although normally NOR uses hot carrier injection for programming, it still has to tunnel (Fowler-Nordheim) to erase. I still call this an injection process, with issues such as SILC. So that is why Flash has the lowest reliability of all memories.
R_Colin_Johnson: Phase-change memory (PRAM) is not "here." Read my comments at the URL you mentioned! Your sister company, UBM Techinsights, was simply the victim of an elaborate scam. The phone unit they tested was a fake, non-commercial unit. Samsung did indeed have PRAM in the original specs for that phone line, but later abandoned PRAM due to power-consumption issues. Thus, it appears, the only cell phone with PRAM in the world was destroyed by UBM Techinsights. You don't believe me? Buy a Samsung GT-E2550 or GT-E2550L Monte Slider and see what's inside. I did. It has NOR and absolutely no PRAM. No commercial product on the market, other than a couple of development boards, uses PRAM or PCM. Please do not perpetuate the Techno-Ponzi!
The article is somewhat misleading in that it says that Flash uses hot electron injection.
NOR flash uses that, but NAND flash uses tunneling, like this memory does. The tunneling gives NAND flash more rewrite cycles than NOR flash as a result, but there’s still a finite lifetime for the NAND flash, ranging from 10,000 cycles (for MLC devices) upwards of 1,000,000 cycles (for the best SLC devices).
In short, I don’t really see the benefit of this technology outside of a few niche applications. In general, it should be possible just to put a DRAM die and a NAND flash on a single package and just write over the DRAM’s contents to the NAND flash when suspending.
On the contrary, phase-change memory (PRAM) is here, although its just substituting for NOR flash so far. Our sister UBM Techinsights reported the world's first use of PRAM was last year:
It still looks to me you will combine the DRAM leakage of first gate with the injection issues of the second NV gate. Whereas the benefits are the same as offered by alternative memories without this issue combination.
Interesting concept though we should wait and see till the final cycling results are actually announced. If it can handle what both Flash and DRAM can do then probably we can work with a single unified memory in the future.
@new2coding. If i understand correctly that was the first thing came in my mind too (I am an industrial PhD student and frequently argue with academic collegues on EEtimes vs IEEtimes :)).
I wonder one day academia learn something from EEtimes/UBM and create perhaps UAM (United Academics Media)or perhaps UBM aciquire IEEE/ACM!:)
You may be right, only time will tell, but the NSF thinks that they at least have a shot of pulling it off. Currently the authors are characterizing the endurance of the architecture, and if it gets over that hurdle, they will address the other doubts you have in mind. Stay tuned for the results, probably in by 2012.
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