Embedded Systems Conference
Breaking News
Comments
Newest First | Oldest First | Threaded View
KarlS
User Rank
Author
re: Another high-level synthesis company targeting FPGAs
KarlS   1/29/2011 7:22:37 PM
NO RATINGS
Hi Dr. DSP This approach requires that binary be generated then transformed into wires and registers in a unique physical pattern with all the placement/routing/timing analysis complications. Why not a design that runs at the source code level so that a few designs with different capacities can be used to cover a range of applications? Just reload the memories to change the function but not the physical layout. That is part of the mpu advantage but debug requires knowing all the processes of the compiler and the cpu instruction set details. Of course the fact that one may have to use C++ rather than C to access the MMIO registers doesn't make anything simpler.

KarlS
User Rank
Author
re: Another high-level synthesis company targeting FPGAs
KarlS   1/29/2011 5:11:59 PM
NO RATINGS
The GCC compiler generates what is called RTL which is then back end compiled to specific cpu instruction sets. I may have the wrong acronym but Wikipedia has a description. Basically two registers are manipulated by an operator and the result put in to a register. Compiler optimization is included, so it sounds like they are putting the registers and data flow operators on the FPGA, bypassing the C to HDL step. Like all the pie in the sky schemes, we will have to wait awhile to see how well it works.

DrFPGA
User Rank
Author
re: Another high-level synthesis company targeting FPGAs
DrFPGA   1/26/2011 7:38:12 PM
NO RATINGS
There is clearly a need to move us up the design ladder to something above pushing signals into registers. I hope these guys can do it- the approach of taking processor code might be a good one...

Max The Magnificent
User Rank
Author
re: Another high-level synthesis company targeting FPGAs
Max The Magnificent   1/25/2011 3:57:21 PM
NO RATINGS
Very interesting Brian -- I used to know some of the folks at AccelChip -- I look forward to discovering more about this BinaChip reincarnation -- Max



Radio
LATEST ARCHIVED BROADCAST
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
Special Video Section
The LTC®6363 is a low power, low noise, fully differential ...
Vincent Ching, applications engineer at Avago Technologies, ...
The LT®6375 is a unity-gain difference amplifier which ...
The LTC®4015 is a complete synchronous buck controller/ ...
10:35
The LTC®2983 measures a wide variety of temperature sensors ...
The LTC®3886 is a dual PolyPhase DC/DC synchronous ...
The LTC®2348-18 is an 18-bit, low noise 8-channel ...
The LT®3042 is a high performance low dropout linear ...
Chwan-Jye Foo (C.J Foo), product marketing manager for ...
The LT®3752/LT3752-1 are current mode PWM controllers ...
LED lighting is an important feature in today’s and future ...
Active balancing of series connected battery stacks exists ...
After a four-year absence, Infineon returns to Mobile World ...
A laptop’s 65-watt adapter can be made 6 times smaller and ...
An industry network should have device and data security at ...
The LTC2975 is a four-channel PMBus Power System Manager ...
In this video, a new high speed CMOS output comparator ...
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...