We have solved critical issue: size the transistors and optimize the circuit using Monte Carlo Simulation based optimization. It will solve many issues related to manual designs.
Reached very high yield optimizing over multiple process corners.
Product Overview: bit.ly/ago-pronov
thank you Frank, excellent clarification...there is probably no pure digital ASICs anymore today as high-speed IOs are always present event on very digital parts...and there are few pure analog ICs as well, modern analog requires digital control or tuning...but as you say there is a big difference between big D little A and little D big A. In the companies I worked for or with design methodologies are very different in both cases...dr Kris
Excellent article Bob. I'd like to add a couple more AMS myths to your list:
Myth #8: Some ICs are pure digital.
No, every IC is analog/mixed-signal. Some are overwhelmingly "Big D, Little A" -- a microprocessor, for example -- others are "Big A, Little D" and there is a large continuum of in-betweens. At a minimum, what some might call a pure digital IC contains at least I/O buffers, which might come from a vendor's library or might be hand-crafted. Either way, those are analog cells.
Myth #9: "Big D, Little A" and "Big A, Little D" ICs are designed using the same tools and methodology.
No, there is a Big D digital-oriented methodology in which analog cells are treated like white boxes and logic cells go everywhere else, and there is a Big A analog-oriented methodology in which everything is a cell, including large blocks of logic cells. The tools are different, the methodology is different, even the mindset of how to assemble the chip is different.
To @Kiran: mixed-signal manufacturing process would typically contain additional layers/masks for analog features: double poly for poly-to-poly capacitors (or MiM capacitors), high resistance poly (or salicide exclusion), HV layers, etc...dr Kris
Making mixed signal ASIC is definitely a challenging task without a right team of analog designers and using the standard cell libraries will not give an optimized ASIC all the time. Would be interesting if you can add some more details regarding the differences in manufacturing process of complete digital ASIC and a mixed signal ASIC with little/significant analog parts.
There are a few mixed signal programmable devices out there that may be sufficient for small quantities or proof of concept. Cypress PSoC is one of these and I am sure there will be more of these types of devices in the future. While these devices may not give the ultimate silicon integration, since they are off the shelf they may be less expensive in the long run and/or get you to market quicker while you are spinning the ASIC.
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