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Warren3
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re: Xilinx CTO: FPGA can drive the crossover SoC
Warren3   2/8/2011 7:06:15 PM
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Xilinx can't chew gum and walk at the same time?

TingLu
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re: Xilinx CTO: FPGA can drive the crossover SoC
TingLu   2/4/2011 4:42:59 PM
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It is wrong impression that FPGA consume more power. It all depends what you are comparing with. If you try to implement the some FPGA features into software running ARM or similar processors, you will use 10x if not 100x more power.

TingLu
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re: Xilinx CTO: FPGA can drive the crossover SoC
TingLu   2/4/2011 4:38:59 PM
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Will you be willing to share your use case such as image format, type of video processing algorithms, and memory bandwidth requirement?

dyson
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re: Xilinx CTO: FPGA can drive the crossover SoC
dyson   2/4/2011 9:13:35 AM
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The comments about yield are spot on but does nobody care about power consumption any more? I think not! There are much better alternatives to FPGA for flexible hardware on SoC.

elPresidente
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re: Xilinx CTO: FPGA can drive the crossover SoC
elPresidente   2/4/2011 2:22:17 AM
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Perhaps fixing the dismal yield Xilinx apparently has on large die might be a better alternative than going for 3D chip rocket science?

Patk0317
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re: Xilinx CTO: FPGA can drive the crossover SoC
Patk0317   2/3/2011 11:22:10 AM
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I first heard about this concept at FPT in Beijing last year. It sounds good, but I will wait and see how it is implemented and what the overall cost is. It will probably fly for some high performance apps where cost is not an issue, but let's see how far down the cost curve this idea goes before making a final judgment.

goafrit
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re: Xilinx CTO: FPGA can drive the crossover SoC
goafrit   2/3/2011 1:26:59 AM
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The challenge is performance. This is not a new concept. The key part is finding a mass market strategy for this. Until they have a product, they will not ascertain the market appeal.

_hm
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re: Xilinx CTO: FPGA can drive the crossover SoC
_hm   2/3/2011 12:10:42 AM
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There are plenty of applications for this basic concept of FPGA cross over for SoC. However, we have not seen any practical implementation. One urgent requirement is SoC with FPGA for video processing of CMOS image sensor with HDMI output. Can Xilinx take lead and provide some demonstration for this? This may be again suited for medium volume application. For high volume application, it may not be cost effective.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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