Nearly 15 years ago we developed various metal pillar ( Au, Cu ) flip Chip technologies at Motorola Semiconductor and put them into mass production for GaAs PAs used in Moto Cell phones. Later developed Cu pillar FC for Si at Intel & Tessera. OSATs like Amkor used by Micrel pretty much use the same technologies now.
Though I agree with the claims in the Micrel article about the improved RDSO for their new FC pkg, I am a little perplexed by their claims about better heat dissipation compared to traditional WB / DB pkg where the heat transfer would be through the whole backside of the die and theta jc would be lower than FC even w/ Cu pillar ( unless they were using really poor conductors like un-loaded epoxies for die bond ).
Dr Dev G.
This discussion is about improved thermal performance and the benefits.
It has nothing to do with off the wall application of wire bond on Cu pillar for some parts. Great solution if it sells more of the same.
The reality is thermal performance is improved as is electrical performance and the die design has the ability to shrink as a result
This article leaves a lot of questions unanswered (or should I say it skips many details?)... the Cu pillar technology is a variant of the flip chip technology which has been around now for decades (stemming from IBM's original C4 concept). Shorter interconnects and interconnecting any where on the chip (as opposed to predominantly peripheral bonding in case of wire bonds) are well known advantages of flip chip.
@GeneOne: the area reduction in the floor space is marginal when compared to the benefits realized by lower RDS(ON). The passivation opening rules for the bond pads in the chip I/O are almost identical between Cu pillars and wirebonds (in fact, many chip design houses prefer it that so you can keep wire bond as a backup; yes you can do wirebonds to the middle of the chip! see TI Swift products).
What the article leaves out is the metallization details on the chip I/O to mitigate electromigration. This is not trivial depending on the application.
FYI, Amkor, Tessera, all have patents on Cu-pillars and micro bumps.
Dr. MP Divakar
My congratulations to the author, the article has serious merit especially looking at the electrical performance based in the resistance across the connection comparing wire bond to Cu Pillars.
This implementation simultaneously reduces the power required and thus reduces the heat generated by the chip. So its fair to say that in personal electronics the battery will last longer.
This begs the question by some as to the cost of the implementation. The point is that Cu Pillar implementations allow for tighter pitch therefore allowing for shrinks of the die by as much as 50%. This makes possible four times as many chips on the same wafer.
The benifits are, we improve thermal performance, assembly yield, reliability, electrical performance use ¼ or the material per chip at very little added cost to the completed wafer. We also eliminate the cost of wire and wire bond especially gold.
It’s a great strategy for high density consumer and commercial ICs where reducing the thermal budget increasing packaging density and delivering more value is required.
Interesting, but I find the title a little mis-leading. I would have written it as "Using copper pillars to decrease analog IC power dissipation". In addition, power dissipation is not mentioned anywhere in the article.
Is there any cost adder to copper pillar over traditional bonding wires? It is good to improve the power handling ability of analog IC but cost may be a road-block. Any other unseen issue with copper pillar?
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