@Frank Eory, @peter.clarke: good comments! More than ever in the history of chip design, the need to approach SoC design truly as a 'system' has become critical; this means many of the post-GDSII tasks (signal integrity, physical verification, packaging, wafer sort, final test, etc.) have impact on the design and need to be looked at the design stage. Very seldom they fit under the triviality of a Lego block!
Aart de Geus, CEO of Synopsys was the first person I heard use the Lego analogy when describing IP reuse and SoC design. This must have been well over a decade ago.
In my opinion, Lego went downhill when they started introducing themed kits, such as pirate ship kits and space vehicle kits.....for me the whole point was that you could build anything from the generic 2 x 2, 2 x 4 blocks and limited set of other non-application specific bricks.
Also, I assert that Lego is both singular and plural. So you would say: "I have a set of Lego bricks. I play with Lego," and so on.
Which means the title of this article should be Let go of my Lego.
I do like the analogy but it has some serious limitations:
1-Building with Legos is quick and simple, building with SoC is not.
2-Re-building a Lego design is quick and easy, redoing a SoC is not.
3-With SoC you can customize blocks, but not with Legos.
It also works in a number of ways:
1-Standard blocks can be used and reused like USB, serial ports, etc.
2-The blocks "fit together" using standard interfaces.
3-When special blocks are needed often times it just costs money to get them in either Legos or SoCs.
I agree with Frank. The operative buzz words some time ago were "reusable IP", but rarely is the IP reusable exactly for every design. In the digital domain it is more possible than in the analog domain. The value for reusable IP is often as a starting point for more innovative designs so long as you hire engineers who know more than putting Lego-like blocks together.
Although the Lego analogy fits to some degree, it is also quite dangerous. Business managers can wrongly assume that it's relatively predictable and straight-forward to develop a multi-hundred-million gate SoC with multiple digital & analog IP cores in an advanced process technology.
"All you have to do" is license the right IP blocks, get some chip designers to throw them together, some verification engineers to run a few simulations, and some software guys to assemble existing software modules. Oh yeah, and throw it in some kind of package and somehow get the wafers and packaged parts tested.
The schedule & budget should be totally predictable, there should be no surprises along the way, first silicon should work perfectly and sail smoothly into mass production...and somehow the product will be differentiated from what your competitors are doing.
SoC design would be very boring if it were that easy!
NASA's Orion Flight Software Production Systems Manager Darrel G. Raines joins Planet Analog Editor Steve Taranovich and Embedded.com Editor Max Maxfield to talk about embedded flight software used on the Mars on EE Times Radio. Live radio show and live chat. Get your questions ready.