@RickMerrit: thanks for the writeup, didn't see you at the Computer History Museum for the 40th Anniversary of Spice event (most ISSCC attendees made it there!).
I wonder why IBM isn't using their Power7 platform to push the clock speeds instead of the z196. The Power6 older generation was already clocking at 4.5GHz whereas Power7 had already reached 5.0GHz (8-core version?). The Power7 also has a L3 cache of 32Mb max.
I strongly suspect Rick is right. Out of order techniques don't yield 40% perf improvements across the board, all by themselves. 20 - 25%, maybe. How well the compiler understands the new, complex microarch is another strong factor. After that you have cache design, bus design, policies on TLB usage, provisions for coherence, and how aggressive you were on lots of other things.
Actually it is good to see an edging up on the frequency. The move to an out-of-order design (40% improvement) is a key advancement along with an increase of 18% in frequency.
I would expect the frequency might edge up a little more over time with the same basic design, but the "step" function of 40% for OOE is the kicker..
I actually know something about both projects, ex-IBMer and ex-MIPS executive..
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.