Parsing the HDL and using embedded memory blocks for control logic and registers to execute the HDL is probably possible using today's FPGA's. It sounds a bit outlandish, but since the memories can cycle in less than half the cycle of a typical FPGA, then one memory can decode the controls to get addresses for 2 operands and have them ready to be used at the end of the main clock cycle just as if they were in discrete registers and gated thru the usual data path. I would need to know more about the need for cycle accuracy requirements to really be sure. A crisper definition of what really constitutes the "System" in ESL would help. i.e. Is there a cpu with an operating system so the communication is via MMIO/Interrupts between the software and hardware, or is there direct connection that must happen on a cycle by cycle basis? (In other words, is the cpu on chip with direct connections?)
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.